Extend the list of modules and assign code owners to each of them.
Change-Id: I267b87d8e239c7eff143b4c7e6ce9712fcf7101e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.
TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.
Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.
Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>
Fixed build error for dualroot chain of trust.
Build error were thrown as below while compiling the code for
dualroot chain of trust:
aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.bss.auth_img_flags+0x0): multiple definition of `auth_img_flags';
./build/fvp/debug/bl1/cot.o:(.bss.auth_img_flags+0x0): first defined here
aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.rodata.cot_desc_size+0x0): multiple definition of `cot_desc_size';
./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_size+0x0): first defined here
aarch64-none-elf-ld.bfd: ./build/fvp/debug/bl1/tbbr_cot_bl1.o:
(.rodata.cot_desc_ptr+0x0): multiple definition of `cot_desc_ptr';
./build/fvp/debug/bl1/cot.o:(.rodata.cot_desc_ptr+0x0): first defined here
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I1a426c4e7f5f8013d71dafc176c7467c1b329757
This patch fixes wrong ID_AA64DFR0_EL1 register read instead of
ID_AA64PFR0_EL1 to detect support for MPAM extension.
It also implements get_mpam_version() function which returns
MPAM version as:
0x00: None Armv8.0 or later;
0x01: v0.1 Armv8.4 or later;
0x10: v1.0 Armv8.2 or later;
0x11: v1.1 Armv8.4 or later;
Change-Id: I31d776b1a1b60cb16e5e62296d70adb129d7b760
Reported-by: Matteo Zini <matteozini96@gmail.com>
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Document the second argument of the function.
Minor rewording.
Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
PSCI demands that SYSTEM_OFF must not return. While it seems like a
generic ATF bug that this is possible when a platform does not Implement
a corresponding handler, let's do that here until it's addressed
differently.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I4c08948b18bbfdc3a24214f2ae0fbad9e017ada1
- Fix possible run-time ELs value and xlat-granule size.
- Remove mandatory field for stream-ids.
- Define interrupts attributes to <u32>.
- Remove mem-manage field.
- Add description for memory/device region attributes.
Co-authored-by: Manish Pandey <manish.pandey2@arm.com>
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I71cf4406c78eaf894fa6532f83467a6f4110b344
SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA FF-A(in documents)
or simply FFA(in code).
Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760
Signed-off-by: J-Alves <joao.alves@arm.com>
We query the UART base address and clk frequency in runtime
using fconf getter APIs.
Change-Id: I5f4e84953be5f384472bf90720b706d45cb86260
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This patch introduces the populate function which leverages
a new driver to extract base address and clk frequency properties
of the uart serial node from HW_CONFIG device tree.
This patch also introduces fdt helper API fdtw_translate_address()
which helps in performing address translation.
Change-Id: I053628065ebddbde0c9cb3aa93d838619f502ee3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.
* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events
Verified using TFTF SDEI test suite.
******************************* Summary *******************************
Test suite 'SDEI' Passed
=================================
Tests Skipped : 0
Tests Passed : 5
Tests Failed : 0
Tests Crashed : 0
Total tests : 5
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390
This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.
The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d
Query the GICD and GICR base addresses in runtime using fconf getter
APIs.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I309fb2874f3329ddeb8677ddb53ed4c02199a1e9
Removing FPEXC32_EL2 from the register save/restore routine for EL2
registers since it is already a part of save/restore routine for
fpregs.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I5ed45fdbf7c8efa8dcfcd96586328d4f6b256bc4
This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.
Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c
and tbbr_cot_bl2.c respectively.
Common CoT used across BL1 and BL2 are moved to
tbbr_cot_common.c.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
This patch sets ENABLE_STACK_PROTECTOR=strong and implements
the platform support to generate a stack protection canary value.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ia8afe464b5645917b1c77d49305d19c7cd01866a
This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.
Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instruction using out-of-context
translation regime.
Workaround is implemented as below during EL's (EL1 or EL2)
"context_restore" operation:
1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1
bits for EL1 or EL2 (stage1 and stage2 disabled)
2. Save all system registers except TCR and SCTLR (for EL1 and EL2)
3. Do memory barrier operation (isb) to ensure all
system register writes are done.
4. Restore TCR and SCTLR registers (for EL1 and EL2)
Errata details are available for various CPUs as below:
Cortex-A76: 1165522
Cortex-A72: 1319367
Cortex-A57: 1319537
Cortex-A55: 1530923
Cortex-A53: 1530924
More details can be found in mail-chain:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html
Currently, Workaround is implemented as build option which is default
disabled.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0
The maintainers.rst file provides the list of all TF-A modules and their
code owners. As there are quite a lot of modules (and more to come) in
TF-A, it is sometimes hard to find the information.
Introduce categories (core code, drivers/libraries/framework, ...) and
classify each module in the right one.
Note that the core code category is pretty much empty right now but the
plan would be to expand it with further modules (e.g. PSCI, SDEI, TBBR,
...) in a future patch.
Change-Id: Id68a2dd79a8f6b68af5364bbf1c59b20c05f8fe7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
Olivier Deprez
Mark Dykes
Manish Pandey
Usama Arif
Manish V Badarkhe
Alexei Fedorov
Jan Kiszka
Louis Mayencourt
J-Alves
Jacky Bai
Madhukar Pappireddy
Varun Wadekar
johpow01
laurenw-arm
Max Shvetsov
Balint Dobszay
joanna.farley