A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.
The new format of SMC procotol will be started
using by Zephyr.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I01cff2739364b1bda2ebb9507ddbcef6095f5d29
SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc
This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.
The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21
HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE
This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f
This patch fixes the code issue detected by Klocwork scan. Pointer
'bl_mem_params' returned from call to function 'get_bl_mem_params_node'
may be NULL and the NULL pointer may be caused the system crash. Update
the code to assert if unexpected NULL pointer is returned.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Change-Id: I00f3132a6104618cadce26aa303c0b46b5921d5b
Request ownership and direct access to QSPI by default in BL2.
Previously, this is only done on QSPI boot mode.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie222bbf9d719f2f70f89d4739c285efe6df4c955
Create a dedicated static struct mmc_device_info mmc_info mmc_info
instead of having this in stack.
A boot issue has been seen on some platform when applying patch [1].
[1] 13f3c5166f ("mmc:prevent accessing to the released space in case of wrong usage")
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This initializes the EMAC PHY in both Stratix 10 and Agilex,
without this, EMAC PHY wouldn't work correctly.
Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Platform handoff structure no longer includes boot source selection.
Hence, those settings can now be configured through socfpga_plat_def.h.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If7ec6a03bb25156a6670ebf8f77105c370b553f6
Create a function to check for fpga readiness, and move the checking out
of bridge enable function.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f473ffeffa9ce181a48977560c8bda19c6123c0
Refactored system manager driver to be shared across both intel platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
Refactor reset manager into intel common platform directory as it can be
shared by both Stratix 10 and Agilex. Register address and field is now
referred through macros.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Id6d50f2a2f5a6bd8d6746b84602ac17ec7f6c07a
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
Watchdog driver support & enablement during platform setup
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
MMC stack needs OCR voltage information for the platform to initialize
MMC controller correctly.
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change map region for device 2 from non-secure to secure
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Sieu Mun Tang
Madhukar Pappireddy
Boon Khai Ng
Siew Chin Lim
Abdul Halim, Muhammad Hadi Asyrafi
Yann Gautier
Sandrine Bailleux
Andre Przywara
Tien Hock, Loh
Dimitris Papastamos