Commit Graph

338 Commits

Author SHA1 Message Date
Venkatesh Yadav Abbarapu 2c791499c2 feat(versal): add UART1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ifcd3c331cf6ce4afb0074357c92fc4addb9438b6
2021-12-22 03:56:42 -07:00
Venkatesh Yadav Abbarapu ea66e4af0b feat(zynqmp): add uart1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I08f69b65b78b967ceb7159f4a467aa5982b1f791
2021-12-22 03:56:16 -07:00
Venkatesh Yadav Abbarapu 67abd4762b feat(plat/zynqmp): disable the -mbranch-protection flag
With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP uses the ARMv8 architecture,
so there is no impact when we disable the branch protection.
These instructions do not provide the branch protection in
architectures before Armv8.3-A.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I36f7a55abf99f50df2ee265255598d83b1f480c6
2021-12-10 05:16:07 -07:00
Abhyuday Godhasara 93d4625627 fix(plat/xilinx/versal): resolve misra R10.6
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
  with wider essential type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Ia0d13c3cfeb13d22b6fc7e8869cc713218302973
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara a62c40d427 fix(plat/xilinx/versal): resolve misra R14.4
MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
  expression of an iteration-statement shall have essentially Boolean type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I8cf821a42015858200cc0c514600012c8f61061f
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 526a1fd147 fix(plat/xilinx/versal): resolve misra R17.7
MISRA Violation: MISRA-C:2012 R.17.7
- The value returned by a function having non-void return type shall be
  used ((void) missing for discarded return value.).

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I1e6a598b9fe6c571a3e5010ee832ef860dfe491d
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara b2bb3efb8f fix(plat/xilinx/versal): resolve misra R10.3
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
  narrower essential type or of a different essential type category

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I9c6dd8dba40db8067b46947ceff295732648612a
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 0623dcea0f fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
  represented in an unsigned type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara bc2637e379 fix(plat/xilinx/versal): resolve misra R15.7
MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated with an else statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iea32e32b5683f7accd7fac8d557957f05ed0f5c5
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara b9fa2d9fc1 fix(plat/xilinx/versal): resolve misra R15.6
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: If1ccaa2f254ac85a329295de501e2b5558e8ff43
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 775bf1bbd3 fix(plat/xilinx/versal): resolve misra R10.1 in pm services
MISRA Violation: MISRA-C:2012 R.10.1
- Operands shall not be of an inappropriate essential type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67b5788054a136be8d764472c5d85528a5c4272f
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 5dada6227b fix(plat/xilinx/versal): resolve misra R20.7 in pm services
MISRA Violation: MISRA-C:2012 R.20.7
- Expressions resulting from the expansion of macro parameters shall be
  enclosed in parentheses

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Id913c556cab955c798809ad2bd08ca3e48e2231a
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 5d1c211e22 fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
  narrower essential type or of a different essential type category

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I73c056ff4df2f14e04c92a49ac5c97e578e82107
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara fa98d7f2f8 fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
  with wider essential type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67ac6b6b4b643f57e76a435345540e241c9a88b9
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 27ae531088 fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I576b2c6eb7d1b7ef20440b9a616886ccf230b63e
2021-11-30 01:59:34 -08:00
Abhyuday Godhasara 4156719550 fix(plat/xilinx/versal): resolve misra R15.6 in pm services
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I82e924a77ee3afeb56fa18714e94cc4f6fff5a49
2021-11-30 01:54:51 -08:00
Scott Branden 4ce3e99a33 fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.

Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2021-11-08 14:41:17 +00:00
Ronak Jain 578f468ac0 feat(plat/xilinx/zynqmp): add support for runtime feature config
Add support for runtime feature configuration which are running on the
 firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and
 IOCTL_GET_FEATURE_CONFIG for configuring the features.

Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I976aef15932783a25396b2adeb4c8f140cc87e79
2021-08-18 22:27:05 -07:00
Ronak Jain 38c0b2521a feat(plat/xilinx/zynqmp): sync IOCTL IDs
Sync IOCTL IDs in order to avoid conflict with other components like,
 Linux and firmware. Hence assigning value to IDs to make it more
 specific.

Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Change-Id: I11ae679fbd0a953290306b62d661cc142f50dc28
2021-08-18 22:23:29 -07:00
Madhukar Pappireddy be3a51ce18 Merge "feat(plat/versal): add support for SLS mitigation" into integration 2021-08-13 17:22:12 +02:00
Venkatesh Yadav Abbarapu 62f9134de0 revert(plat/xilinx): add timeout while waiting for IPI Ack
This reverts commit 4d9b9b2352.

Timeout in IPI ack was added for functional safety reason.
Functional safety is not criteria for ATF. However, this
creates issues for APIs that take long or non-deterministic
duration like FPGA load. So revert this patch for now to fix
FPGA loading issue. Need to add support for non-blocking API
for FPGA loading with callback when API completes.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I940e798f1e2f7d0dfca1da5caaf8b94036d440c6
2021-08-09 23:20:39 -06:00
Venkatesh Yadav Abbarapu 302b4dfb8f feat(plat/versal): add support for SLS mitigation
This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2
2021-07-20 22:33:47 -06:00
Abhyuday Godhasara fa58171534 fix(plat/xilinx/versal): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I6f568b85d0da639c264f507122e3015807d8423d
2021-07-08 05:29:50 -07:00
Abhyuday Godhasara c063c5a4f9 fix(plat/xilinx/zynqmp): use sync method for blocking calls
All API calls except non-blocking should wait for
IPI response and read buffer to check return status
from firmware. Some of API calls are not reading
status from IPI payload data. Use sync method which
reads actual return status from IPI payload.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I78f9c061a80cee6d524ade4ef124ca88ce1848cf
2021-07-08 05:23:41 -07:00
Madhukar Pappireddy a43179a694 Merge "feat(plat/zynqmp): extend DT description by TF-A" into integration 2021-07-07 16:08:51 +02:00
Venkatesh Yadav Abbarapu db97f93963 refactor(plat/zynqmp): optimize the code to save some space
As there is constraint with the space for the release builds,
remove some of the legacy code.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852
2021-06-17 00:43:41 -06:00
Michal Simek 0a8143dd63 feat(plat/zynqmp): extend DT description by TF-A
In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can be (and should be) also protected by
protection unit XMPU. This is the first step to add reserved
memory location to DT.

DT address corresponds with default address in U-Boot and also
default address in Xilinx BSPs.

Code is valid only when TF-A runs out of DDR. When it runs out
of OCM there is no need to reseve anything because OCM is hidden
to OS.

Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-14 09:33:37 +02:00
Jan Kiszka 4143268a5c feat(plat/zynqmp): add SDEI support
Add basic SDEI support, implementing the software event 0 only for now.
This already allows hypervisors like Jailhouse to use SDEI for internal
signaling while passing the GICC through to the guest (see also IMX8).

With SDEI on, we overrun the SRAM and need to stay in DRAM. So keep SDEI
off by default.

Co-developed-by: Angelo Ruocco <angeloruocco90@gmail.com>
Signed-off-by: Angelo Ruocco <angeloruocco90@gmail.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: Ic0d71b4ef0978c0a34393f4e3530ed1e24a39ca2
2021-06-03 16:34:12 +02:00
Venkatesh Yadav Abbarapu 7a30e08b70 feat(plat/zynqmp): add support for XCK26 silicon
Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338
2021-05-30 21:37:20 -06:00
Rajan Vaja e1e5b1339b fix(plat/xilinx/versal/include): correct IPI buffer offset
Use proper offset for IPI data based on offset for IPI0
channel.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I3070517944dd353c3733aa595df0da030127751a
2021-05-25 07:02:49 -07:00
Venkatesh Yadav Abbarapu 78c7beb49c plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
2021-04-22 22:47:17 +02:00
Shubhrajyoti Datta 8b48bfb897 plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: I9c04fdae7be3dda6a34a9b196274c0b5fdf39223
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
2021-04-22 22:47:12 +02:00
Manish Pandey d8dc8c9e2e Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration 2021-04-21 16:48:32 +02:00
Rajan Vaja 9f0ddae317 plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
2021-04-21 12:29:37 +02:00
Venkatesh Yadav Abbarapu 654bd99dc6 plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
2021-04-21 12:19:32 +02:00
Venkatesh Yadav Abbarapu d77583549f plat: xilinx: common: Rename the IPI CRC checksum macro
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58
2021-04-21 12:19:25 +02:00
Venkatesh Yadav Abbarapu 0b25f4045a plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
2021-03-31 22:00:21 -06:00
Venkatesh Yadav Abbarapu c00baeecbb plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
2021-03-31 22:00:04 -06:00
Tejas Patel 4697164a3f plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.

Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
2021-03-19 07:47:12 -07:00
Madhukar Pappireddy 0888fcf252 Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration 2021-03-18 15:15:11 +01:00
Madhukar Pappireddy 0fb7363899 Merge "plat: xilinx: Add timeout while waiting for IPI Ack" into integration 2021-03-18 14:15:48 +01:00
Michal Simek 4a7b060b3d plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
2021-03-16 13:17:37 +01:00
Venkatesh Yadav Abbarapu 1b7e5ca998 plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
2021-03-03 00:49:39 -07:00
Tejas Patel 4d9b9b2352 plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
2021-03-01 20:26:59 -08:00
Venkatesh Yadav Abbarapu 830774bfd0 plat:xilinx:zynqmp: Remove the custom crash implementation
Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I045d42eb62bcaf7d1e18fbe9ab9fb9470e800215
2021-02-23 20:06:53 -07:00
Rajan Vaja f621d5fb4b plat: xilinx: versal: Remove code duplication
Some switch cases uses same operation. So, club switch cases
which uses same operation and remove duplicate code.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
2021-01-20 00:59:33 -08:00
Will Wong 0a67923b99 zynqmp: pm: Add support for PS and system reset on WDT restart
Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.

Signed-off-by: Will Wong <willw@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702
2021-01-12 16:59:55 +00:00
Rajan Vaja 19fe3c7295 zynqmp: pm: Update PM version and support PM version check
ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ia095d118121e6f75e8d320e87d5e2018068fa079
2021-01-11 21:34:40 -08:00
Venkatesh Yadav Abbarapu e43258fa00 plat: xilinx: Fix non-MISRA compliant code
This patch fixes the non compliant code like missing braces for
conditional single statement bodies.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I95b410ae5950f85dc913c4448fcd0a97e0fd490c
2021-01-10 20:48:09 -07:00
Manish Pandey 24ca0fa6ac Merge changes from topic "xilinx-sd-tap-delay" into integration
* changes:
  plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
  plat: zynqmp: Check for DLL status before doing reset
2021-01-06 12:23:10 +00:00