Commit Graph

1467 Commits

Author SHA1 Message Date
Siva Durga Prasad Paladugu 91bf4c5c15 zynqmp: Fix EG/EV detection logic
The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, display
EG/EV as a part of string. The PL powerup status will
be filled by pmufw based on PL PROGB status in the
9th bit of version field.This patch also used IPI
to get this info from pmufw instead of directly accessing
the registers. Accessing this info from pmufw using
IPI fixes the issue of PMUFW access denied error for
reading IPDISABLE register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-05-17 15:19:23 +05:30
Siva Durga Prasad Paladugu 5479fa704b zynqmp: Add new API for processing secure images
This patch adds new API for processing secure images. This API
is used for authentication and decryption of secure images using
xilsecure in pmufw.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:19:19 +05:30
Tejas Patel 7dae6137ef xilinx: zynqmp: pm_service: Fix APU only restart
Existing code blocks each IPI send request in ipi_mb_notify()
function till pmu clears respective bit in ipi observation
register.

After sending PM_SYSTEM_SHUTDOWN request to PMU, PMU will
restart APU. While PMU is restarting APU, ATF is running out
of OCM, which can cause read/write hang from/to OCM.
There is no need to wait for notification from PMU in case
of SystemShutdown request in ATF, as APU is going to restart.

This patch fixes APU only restart issue.

Signed-off-by: Tejas Patel <tejasp@xilinx.com>
Acked-by: Wendy Liang <wendy.liang@xilinx.com>
2018-05-17 15:19:14 +05:30
Siva Durga Prasad Paladugu 3f0d4f1bd5 plat: xilinx: zynqmp: Make fpga load blocking until completed
This patch makes bitstream load blocking call and waits until
bitstream is loaded successfully or return with error.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Avesh Khan <aveshk@xilinx.com>
2018-05-17 15:19:10 +05:30
Siva Durga Prasad Paladugu b84fb058bb plat: xilinx: zynqmp: Remove GET_CALLBACK_DATA function
GET_CALLBACK_DATA function is not required now. IPI mailbox
can be used instead of GET_CALLBACK_DATA function.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:19:07 +05:30
Rajan Vaja 85dc2d4dae zynqmp: pm_service: Make PMU IPI-1 channel unsecure
PMU IPI-1 is used for callbacks from PMU to master. Unsecure
master can also receive callbacks from PMU, so make PMU IPI-1
as non-secure.

All requests from master(s) to PMU would still go on PMU IPI-1
secure channel.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
2018-05-17 15:19:02 +05:30
Rajan Vaja 88d02c4aea zynqmp: pm: Remove unnecessary header includes
Remove includes of gic_common.h and string.h which
are not required.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Acked-by: Jolly Shah <jollys@xilinx.com>
2018-05-17 15:18:53 +05:30
Siva Durga Prasad Paladugu a6d28520b5 xilinx: zynqmp: Remove PMU Firmware checks
Xilinx now requires the PMU FW when using ATF, so it doesn't make sense
to maintain checks for the PMU FW in ATF. This also means that cases
where ATF came up before the PMU FW (such as on QEMU) ATF will now hang
waiting for the PMU FW instead of aborting.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2018-05-17 15:18:46 +05:30
Siva Durga Prasad Paladugu 3d512f0b32 zynqmp: pm: Reverse logic for detecting that the PMU firmware is loaded
Use positive logic (pm_up instead of pm_down) to check whether PMU
services are available. This change also puts the variable into the
BSS section rather than the Data section as the variable is now
initialized to 0 rather than 1.

Signed-off-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:18:42 +05:30
Alistair Francis 756e7f2825 plat: zynqmp: Don't panic() if we can't find the FSBL struct
If we can't find the FSBL handoff struct don't panic and just use the
defaults instead.

We still print a warning to the user to let them know what we couldn't
find it.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-05-17 15:18:32 +05:30
Siva Durga Prasad Paladugu b116048055 plat: zynqmp: Let fsbl_atf_handover() return an error status
Instead of calling panic() in fsbl_atf_handover() return the error
status so that bl31_early_platform_setup() can act accordingly.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:17:46 +05:30
Wendy Liang b88b0c9fff Include "bl_common.h" in Xilinx zynqmp_private.h
Type "entry_point_info_t" is used in zynqmp_private.h. It is defined
in "bl_common.h". The header file which defines the type should be
included.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
2018-05-17 15:13:03 +05:30
Siva Durga Prasad Paladugu c95b2dfae4 zynqmp: pm: Added APIs for xilsecure linux support
Added SHA to calculate SHA3 hash,RSA to encrypt data with
public key and decrypt with private key and AES to do symmetric
encryption with User key or device key.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:12:59 +05:30
Siva Durga Prasad Paladugu 915d4872cb plat: zynqmp: Add support for CG/EG/EV device detection
Read ipdisable reg which needs to be used for cg/eg/ev device detection.
ATF runs in EL3 that's why this read can be done directly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:12:56 +05:30
Siva Durga Prasad Paladugu d9710aeb03 aarch64: zynqmp: Add new Ids for RFSoC
Add new id codes for RFSoC's.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-17 15:12:52 +05:30
Siva Durga Prasad Paladugu e27d3b59b5 zynqmp: Fix CSU ID SVD mask fo getting chip ID
This patch corrects the SVD mask for getting chip ID
using 0xe is wrong and 0x7 is correct.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2018-05-17 15:12:47 +05:30
Siva Durga Prasad Paladugu 61ef376aa2 zynqmp: pm: Allow to set shutdown scope via pm_system_shutdown API
psci system_reset and system_off calls now retrieve shutdown scope on
the fly. The default scope is system, but it can be changed by calling
pm_system_shutdown(2, scope)

Until full support for different restart scopes becomes available with
PSCI 1.1 this change allows users to set the reboot scope to match
their application needs.

Possible scope values:
0 - APU subsystem: does not affect RPU, PMU or PL
1 - PS only: shutdown/restart entire PS without affecting PL
2 - System: shutdown/restart applies to entire system

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
2018-05-17 15:12:44 +05:30
Filip Drazic 27722ac1b0 zynqmp: pm: Implement PM_INIT_FINALIZE PM API call
The PM_INIT_FINALIZE PM API is required to inform the PFW that APU is
done with requesting nodes and that not-requested nodes can be powered
down. If PM is not enabled, this call will never be made and PFW will
never power down any of the nodes which APU can use.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2018-05-17 15:12:25 +05:30
Filip Drazic 0484967207 zynqmp: pm: Rename PM_INIT to PM_INIT_FINALIZE
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2018-05-17 15:12:19 +05:30
Siva Durga Prasad Paladugu e71fe2a3f2 zynqmp: pm: Implemented new pm API to load secure images
This patch adds pm_secure_rsaaes() API to provide access to
the xilsecure library for loading secure images

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-05-17 15:12:14 +05:30
Siva Durga Prasad Paladugu 29bd0e6688 xilinx: zynqmp: Read bootmode register using PM API
Read boot mode register using pm_mmio_read if pmu is
present otherwise access it directly using mmio_read_32().

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2018-05-17 15:12:08 +05:30
Filip Drazic 0b3a4e414b zynqmp: pm: Decode start address related SMC arguments for pm_req_wakeup
The pm_req_wakeup PM API accepts start address (64-bit unsiged integer)
and a flag stating if address should be used. To save an argument
of the SMC call, flag is encoded in the LSB of the address, since
addresses are word aligned.
Decode start address and use-address flag in the PM SMC handler and
pass them to pm_req_wakeup.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
2018-05-17 15:12:02 +05:30
Filip Drazic 9feba2e7dd zynqmp: pm: Move pm_client_wakeup call from pm_req_wakeup
Call to pm_client_wakeup from pm_req_wakeup prevented the PM API
call to be used to wake up non-APU processor (e.g. from higher ELs),
since it clears power down request for specified APU processor.
Move this function out of pm_client_wakeup to allow passing wake up
requests to the PMU for other processor in the system.

Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
2018-05-17 15:11:52 +05:30
Mirela Simonovic c496f5af54 zynqmp: pm: Remove unused NODE_AFI, add NODE_EXTERN
NODE_EXTERN is the slave node which represents an external wake
source.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
2018-05-17 15:11:44 +05:30
Siva Durga Prasad Paladugu 34c571392e zynqmp: pm: Add support for setting suspend-to-RAM mode
Beside standard suspend-to-RAM state, Zynq MPSoC supports
suspend-to-RAM state with additional power savings, called
power-off suspend-to-RAM. If this mode is set, only NODE_EXTERN
must be set as wake source. Standard suspend-to-RAM procedure
is unchanged.

This patch adds support for setting suspend mode from higher
ELs and ensuring that all conditions for power-off suspend mode
are set.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
2018-05-17 15:11:33 +05:30
Anes Hadziahmetagic d744b6f56f zynqmp: pm: Implement pm_get_node_status API function
pm_get_node_status API function returns 3 values:
-status: Current power state of the node
-requirements: Current requirements for the node
-usage: Current usage of the node
The last two values only apply to slave nodes.

Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com>
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
2018-05-17 15:11:27 +05:30
Dimitris Papastamos b6ceca4303
Merge pull request #1387 from vishwanathahg/sgi575/core_pos_calc
Sgi575/core pos calc
2018-05-16 15:23:18 +01:00
Dimitris Papastamos dcf1a04e3b
Merge pull request #1381 from antonio-nino-diaz-arm/an/kernel-boot
plat/arm: Introduce ARM_LINUX_KERNEL_AS_BL33 build option
2018-05-16 14:26:28 +01:00
Vishwanatha HG 8aaa8634a3 css/sgi: rework the core position calculation function
The MT bit in MPIDR is always set for SGI platforms and so the
core position calculation code is updated to take into account
the thread affinity value as well.

Change-Id: I7b2a52707f607dc3859c6bbcd2b145b7987cb4ed
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Vishwanatha HG <vishwanatha.hg@arm.com>
2018-05-16 12:11:41 +05:30
Vishwanatha HG 8ac176585a css/sgi: remove redundant copy of gic driver data
Instead of instantiating a local copy of GICv3 driver data for SGI
platforms, reuse the existing instance of GICv3 driver data available
in the arm common platform code.

Change-Id: If6f38e15d1f0e20cea96fff98091da300015d295
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Vishwanatha HG <vishwanatha.hg@arm.com>
2018-05-16 12:11:34 +05:30
Dimitris Papastamos ede13422f7
Merge pull request #1379 from CJKay/nsram-fix
Fix incorrect NSRAM memory map region for SGI-575
2018-05-15 18:40:03 +01:00
Jeenu Viswambharan e1040aac74 Fix build error with correct format string
Change-Id: I11c12b113c4975efd3ac7ac2e8b93e6771a7e7ff
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-05-15 17:05:36 +01:00
Dimitris Papastamos a513506b07
Merge pull request #1373 from jeenu-arm/ras-support
RAS support
2018-05-15 15:34:20 +01:00
Antonio Nino Diaz bf4698fdef Revert "plat/arm: Migrate AArch64 port to the multi console driver"
This reverts commit 2f18aa1fa3.

It is causing some tests to fail. Until the cause is found and fixed, it
is needed to remove this commit from master.

Change-Id: Ic5ff7a841903a15613e00379e87cbbd8a0e85152
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-15 13:17:55 +01:00
Chris Kay d7ecac73b5 css: Fix erroneous non-secure RAM base address/size for SGI-575
SGI-575's NSRAM is neither in the same place nor the same size as Juno's.

Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823
Signed-off-by: Chris Kay <chris.kay@arm.com>
2018-05-11 15:37:47 +01:00
Antonio Nino Diaz b726c16907 plat/arm: Introduce ARM_LINUX_KERNEL_AS_BL33 build option
Normally, BL33 needs to contain a boot loader like U-Boot or UEFI that
eventually gives control to the OS. However, in some cases, this boot
sequence may be too slow. For example, when doing tests in a
cycle-accurate emulator, the user may only be interested in the
interaction between the Trusted Firmware and the OS, not in the boot
process itself.

The new option ARM_LINUX_KERNEL_AS_BL33 allows BL33 to contain the Linux
kernel image by changing the value of registers x0-x3 to the values
expected by the kernel. This option requires the device tree blob (DTB)
to be present in memory. Its address must be specified in the newly
introduced ARM_PRELOADED_DTB_BASE build option. For now, it only supports
AArch64 kernels.

This option is only available when RESET_TO_BL31=1. For this reason
the BL33 binary must be preloaded in memory and PRELOADED_BL33_BASE must
be used.

For example, if the kernel is loaded at 0x80080000 and the DTB is loaded
at address 0x82000000, the firmware could be built like this:

    CROSS_COMPILE=aarch64-linux-gnu-  \
    make PLAT=fvp DEBUG=1             \
    RESET_TO_BL31=1                   \
    ARM_LINUX_KERNEL_AS_BL33=1        \
    PRELOADED_BL33_BASE=0x80080000    \
    ARM_PRELOADED_DTB_BASE=0x82000000 \
    all fip

Change-Id: If9dc847c65ae2d0c27b51f0fd44fc06b28497db9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-11 11:15:10 +01:00
Antonio Nino Diaz 2f18aa1fa3 plat/arm: Migrate AArch64 port to the multi console driver
The old API is deprecated and will eventually be removed.

Arm platforms now use the multi console driver for boot and runtime
consoles. However, the crash console uses the direct console API because
it doesn't need any memory access to work. This makes it more robust
during crashes.

The AArch32 port of the Trusted Firmware doesn't support this new API
yet, so it is only enabled in AArch64 builds. Because of this, the
common code must maintain compatibility with both systems. SP_MIN
doesn't have to be updated because it's only used in AArch32 builds.
The TSP is only used in AArch64, so it only needs to support the new
API without keeping support for the old one.

Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this
causes the UARTs to reset (except for the one used by the TSP). This
means that they must be unregistered when suspending and re-registered
when resuming. This wasn't a problem with the old driver because it just
restarted the UART, and there were no problems associated with
registering and unregistering consoles.

The size of BL31 has been increased in builds with SPM.

Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-05-11 10:46:58 +01:00
danh-arm 43d71452b2
Merge pull request #1354 from robertovargas-arm/mem_protect
ARM platforms: Demonstrate mem_protect from el3_runtime
2018-05-08 11:21:04 +01:00
Jeenu Viswambharan 0b9ce9064c ARM Platforms: Support RAS
- Assign 0x10 for RAS exceptions on ARM platforms, and install
    EHF priority descriptor.

  - Call the common RAS initialisation from ARM BL31 setup.

  - Add empty definitions for platform error records and RAS interrupts.

Change-Id: I0675f299b7840be4c83a9c7a81073a95c605dc90
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-05-04 08:33:17 +01:00
Jeenu Viswambharan 362599eca4 RAS: Add support for node registration
Previous patches added frameworks for handling RAS errors. This patch
introduces features that the platform can use to enumerate and iterate
RAS nodes:

  - The REGISTER_RAS_NODES() can be used to expose an array of
    ras_node_info_t structures. Each ras_node_info_t describes a RAS
    node, along with handlers for probing the node for error, and if
    did record an error, another handler to handle it.

  - The macro for_each_ras_node() can be used to iterate over the
    registered RAS nodes, probe for, and handle any errors.

The common platform EA handler has been amended using error handling
primitives introduced by both this and previous patches.

Change-Id: I2e13f65a88357bc48cd97d608db6c541fad73853
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-05-04 08:33:17 +01:00
Jeenu Viswambharan 76454abf4a AArch64: Introduce External Abort handling
At present, any External Abort routed to EL3 is reported as an unhandled
exception and cause a panic. This patch enables ARM Trusted Firmware to
handle External Aborts routed to EL3.

With this patch, when an External Abort is received at EL3, its handling
is delegated to plat_ea_handler() function. Platforms can provide their
own implementation of this function. This patch adds a weak definition
of the said function that prints out a message and just panics.

In order to support handling External Aborts at EL3, the build option
HANDLE_EA_EL3_FIRST must be set to 1.

Before this patch, HANDLE_EA_EL3_FIRST wasn't passed down to
compilation; this patch fixes that too.

Change-Id: I4d07b7e65eb191ff72d63b909ae9512478cd01a1
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-05-04 08:32:42 +01:00
danh-arm 9c52bbc035
Merge pull request #1361 from vchong/tool_add_img
poplar: rename FIP_ADD_IMG to TOOL_ADD_IMG
2018-05-01 17:12:51 +01:00
Roberto Vargas 638b034cc3 ARM platforms: Demonstrate mem_protect from el3_runtime
Previously mem_protect used to be only supported from BL2. This is not
helpful in the case when ARM TF-A BL2 is not used. This patch demonstrates
mem_protect from el3_runtime firmware on ARM Platforms specifically
when RESET_TO_BL31 or RESET_TO_SP_MIN flag is set as BL2 may be absent
in these cases. The Non secure DRAM is dynamically mapped into EL3 mmap
tables temporarily and then the protected regions are then cleared. This
avoids the need to map the non secure DRAM permanently to BL31/sp_min.

The stack size is also increased, because DYNAMIC_XLAT_TABLES require
a bigger stack.

Change-Id: Ia44c594192ed5c5adc596c0cff2c7cc18c001fde
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-05-01 15:25:25 +01:00
danh-arm ccd130ea74
Merge pull request #1255 from masahir0y/int-ll64
Use consistent int-ll64 typedefs for aarch32 and aarch64
2018-05-01 15:06:56 +01:00
Masahiro Yamada 0a2d5b43c8 types: use int-ll64 for both aarch32 and aarch64
Since commit 031dbb1224 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch32 and aarch64.

For example, uint64_t is defined as 'unsigned long long' for aarch32
and as 'unsigned long' for aarch64.  Likewise, uintptr_t is defined
as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64.

A problem typically arises when you use printf() in common code.

One solution could be, to cast the arguments to a type long enough
for both architectures.  For example, if 'val' is uint64_t type,
like this:

  printf("val = %llx\n", (unsigned long long)val);

Or, somebody may suggest to use a macro provided by <inttypes.h>,
like this:

  printf("val = %" PRIx64 "\n", val);

But, both would make the code ugly.

The solution adopted in Linux kernel is to use the same typedefs for
all architectures.  The fixed integer types in the kernel-space have
been unified into int-ll64, like follows:

    typedef signed char           int8_t;
    typedef unsigned char         uint8_t;

    typedef signed short          int16_t;
    typedef unsigned short        uint16_t;

    typedef signed int            int32_t;
    typedef unsigned int          uint32_t;

    typedef signed long long      int64_t;
    typedef unsigned long long    uint64_t;

[ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ]

This gets along with the codebase shared between 32 bit and 64 bit,
with the data model called ILP32, LP64, respectively.

The width for primitive types is defined as follows:

                   ILP32           LP64
    int            32              32
    long           32              64
    long long      64              64
    pointer        32              64

'long long' is 64 bit for both, so it is used for defining uint64_t.
'long' has the same width as pointer, so for uintptr_t.

We still need an ifdef conditional for (s)size_t.

All 64 bit architectures use "unsigned long" size_t, and most 32 bit
architectures use "unsigned int" size_t.  H8/300, S/390 are known as
exceptions; they use "unsigned long" size_t despite their architecture
is 32 bit.

One idea for simplification might be to define size_t as 'unsigned long'
across architectures, then forbid the use of "%z" string format.
However, this would cause a distortion between size_t and sizeof()
operator.  We have unknowledge about the native type of sizeof(), so
we need a guess of it anyway.  I want the following formula to always
return 1:

  __builtin_types_compatible_p(size_t, typeof(sizeof(int)))

Fortunately, ARM is probably a majority case.  As far as I know, all
32 bit ARM compilers use "unsigned int" size_t.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-27 18:35:02 +09:00
Masahiro Yamada 57d1e5faf2 Fix pointer type mismatch of handlers
Commit 4c0d039076 ("Rework type usage in Trusted Firmware") changed
the type usage in struct declarations, but did not touch the definition
side.  Fix the type mismatch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-27 18:35:02 +09:00
Dimitris Papastamos a8d9550b52
Merge pull request #1345 from dbasehore/udelay
rockchip/rk3399: Fix sram_udelay
2018-04-26 14:14:28 +01:00
Victor Chong 00ad56e6d9 poplar: rename FIP_ADD_IMG to TOOL_ADD_IMG
Fixes: f3d522b ("poplar: Support Trusted OS extra image (OP-TEE header) parsing")
Signed-off-by: Victor Chong <victor.chong@linaro.org>
2018-04-24 04:43:31 +01:00
Sudipto Paul bb3a6f8c7e css/sgi575: enable ARM_PLAT_MT flag
SGI-575 platform is based on Cortex-A75 processor which has its MT bit
in the MPIDR register set to '1'. So the Arm platform layer code has
to be made aware of this.

Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
2018-04-18 14:19:52 +05:30
Dimitris Papastamos bedf6f0b14
Merge pull request #1250 from jollysxilinx/zynqmp-new-eemi-api
plat/xilinx: Add support for new platform management APIs for ZynqMP
2018-04-17 12:08:34 +01:00