Commit Graph

6385 Commits

Author SHA1 Message Date
Steven Kao a3c2c0e96b Tegra194: config to enable/disable strict checking mode
This patch adds a new configuration option to the platform makefiles
that disables/enables strict checking mode. The config is enabled
by default.

Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb
Signed-off-by: Steven Kao <skao@nvidia.com>
2020-01-17 10:30:40 +00:00
Varun Wadekar 181a9fabce Tegra194: remove unused platform configs
This patch cleans the makefile to remove unused platform config
options.

Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-17 10:30:33 +00:00
Varun Wadekar 26c1a1e769 Tegra194: restore XUSB stream IDs on System Resume
The stream IDs for XUSB programmed during cold boot are lost on System
Suspend. This patch restores the XUSB stream IDs on System Resume.

NOTE: THE WARMBOOT CODE NEEDS TO MAKE SURE THAT THE XUSB MODULE IS OUT
OF RESET AND THE CLOCKS ARE ENABLED, BEFORE POWERING ON THE CPU, DURING
SYSTEM RESUME.

Change-Id: Ibd5f1e5ebacffa6b29b625f4c41ecf204afa8191
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-17 10:29:52 +00:00
Manish Pandey 62ee142531 Merge "rcar_gen3: Add missing #{address,size}-cells into generated DT" into integration 2020-01-17 09:52:14 +00:00
Mark Dykes 38aac6d405 Merge "docs: Creating a Change Log Template File" into integration 2020-01-16 17:24:13 +00:00
Manish Pandey 5d3ee0764b Merge "plat: intel: Fix UEFI decompression issue" into integration 2020-01-15 16:11:56 +00:00
Manish Pandey 9445bc2d33 Merge "intel: Change all global sip function to static" into integration 2020-01-15 16:11:36 +00:00
Tien Hock, Loh 389091a8d6 plat: intel: Fix UEFI decompression issue
UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396
2020-01-15 13:41:34 +00:00
Hadi Asyrafi e5ebe87b6d intel: Change all global sip function to static
All function in socfpga_sip_svc.c should only be called locally except
sip_smc_handler().

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5
2020-01-15 13:31:29 +00:00
Manish Pandey 351ab9f54d Merge "a8k: Implement platform specific power off" into integration 2020-01-15 13:14:09 +00:00
Alexei Fedorov 7bad6e0885 Merge "allwinner: Reenable USE_COHERENT_MEM" into integration 2020-01-15 10:22:57 +00:00
Samuel Holland 6c281cc3a4 allwinner: Reenable USE_COHERENT_MEM
Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
2020-01-15 09:09:41 +00:00
Luka Kovacic 8c11ebfcda a8k: Implement platform specific power off
Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.

Marvell Armada 8K boards can now add a board/system_power.c file
that contains a system_power_off() function.
This function can now send a command to a power management MCU or
other board periferals before shutting the board down.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db
---
I am working on a device that will be ported later, which has a
custom power management MCU that handles LEDs, board power and fans
and requires this separation.
2020-01-15 07:31:43 +01:00
Marek Vasut 6be71b09c9 rcar_gen3: Add missing #{address,size}-cells into generated DT
Add missing #address-cells and #size-cells into generated DT, otherwise
the DT is invalid. While the parsers thus far handled this correctly via
various fallbacks, this is not applicable in the long run, so fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
2020-01-15 05:18:03 +01:00
Manish Pandey e9ed7fa73e Merge changes from topic "sip-svc" into integration
* changes:
  intel: Implement platform specific system reset 2
  intel: Enable SiP SMC secure register access
2020-01-14 22:24:30 +00:00
Manish Pandey 4694e1e78d Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration 2020-01-14 22:00:41 +00:00
Manish Pandey bc3579b7fa Merge "intel: Fix memory calibration" into integration 2020-01-14 18:28:43 +00:00
Olivier Deprez f1c94d1e6a Merge "rpi4: Fix documentation of armstub config entry" into integration 2020-01-14 17:05:27 +00:00
Jan Kiszka 433090515d rpi4: Fix documentation of armstub config entry
It's in fact mandatory. Seen with RPi firmware 1.20190925.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892
2020-01-14 17:04:49 +00:00
Manish Pandey 2aa60e703c Merge "plat: rpi4: Skip UART initialisation" into integration 2020-01-14 14:10:42 +00:00
Manish Pandey 22c2316dfe Merge "console: 16550: Prepare for skipping initialisation" into integration 2020-01-14 14:09:58 +00:00
Sandrine Bailleux 2049b6f994 Merge changes from topic "add-versal-soc-support" into integration
* changes:
  zynqmp: pm: Add LPD WDT clock to the pm_clock structure
  zynqmp: pm: Fix clock models and IDs of GEM-related clocks
  zynqmp: pm: Rename FPD WDT clock ID
  plat: xilinx: zynqmp: Correct syscnt freq for QEMU
  arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
  arm64: zynqmp: Add id for new RFSoC device ZU39DR
2020-01-14 12:50:15 +00:00
Alexei Fedorov f1f8ea20dc Merge "allwinner: Move the NOBITS region to SRAM A1" into integration 2020-01-14 09:04:03 +00:00
Sandrine Bailleux 743600b25c Merge "intel: Remove un-needed checks for qspi driver r/w" into integration 2020-01-13 17:18:30 +00:00
Sandrine Bailleux d5ce8df741 Merge changes from topic "tegra-misra-21.1-fixes" into integration
* changes:
  Tegra194: drivers: fix violations of MISRA Rule 21.1
  Tegra: include: fix violations of MISRA Rule 21.1
2020-01-13 17:16:30 +00:00
Alexei Fedorov dadd8060f1 Merge "docs: GCC toolchain upgrade to version 9.2-2019.12" into integration 2020-01-13 11:06:13 +00:00
Hadi Asyrafi f6c4b19ac8 intel: Remove un-needed checks for qspi driver r/w
This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53
2020-01-13 16:26:40 +08:00
Varun Wadekar 22c72f2a29 Tegra194: drivers: fix violations of MISRA Rule 21.1
This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc
2020-01-12 14:46:04 -08:00
Varun Wadekar 67db323195 Tegra: include: fix violations of MISRA Rule 21.1
This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185
2020-01-12 14:44:40 -08:00
Madhukar Pappireddy f35e5ab39c docs: GCC toolchain upgrade to version 9.2-2019.12
This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I910200174d5bad985504d1af4a1ae5819b524003
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-10 16:12:01 -06:00
Mark Dykes 436367966f Merge "Unify type of "cpu_idx" across PSCI module." into integration 2020-01-10 19:39:17 +00:00
Deepika Bhavnani 5b33ad174a Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
   API `plat_psci_stat_get_residency()` third argument
   `last_cpu_idx` is changed from "signed int" to the
   "unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
2020-01-10 17:11:51 +00:00
Manish Pandey 1522958fcd Merge "rcar_gen3: plat: Pass DT to OpTee OS" into integration 2020-01-10 16:58:56 +00:00
Manish Pandey 13be0ee40f Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration 2020-01-10 16:58:24 +00:00
Mark Dykes 5c33096742 Merge "FVP: Remove re-definition of topology related build options" into integration 2020-01-10 16:42:27 +00:00
Mark Dykes 865054dca8 Merge "FVP: Stop reclaiming init code with Clang builds" into integration 2020-01-10 16:33:59 +00:00
Manish Pandey d71ccda791 Merge "rcar_gen3: drivers: ddr: Move DDR drivers out of staging" into integration 2020-01-10 15:31:04 +00:00
Sandrine Bailleux d11a6057a4 Merge "Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"" into integration 2020-01-10 15:25:47 +00:00
Alexei Fedorov 94f1c9593d FVP: Remove re-definition of topology related build options
This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
 'FVP_CLUSTER_COUNT'
 'FVP_MAX_CPUS_PER_CLUSTER'
 'FVP_MAX_PE_PER_CPU'
which are set in platform.mk.

This fixes a potential problem when a build option set in
platform.mk file can be re-defined in fvp_def.h header file
used by other build component with a different makefile which
does not set this option.
Ref. GENFW-3505.

Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-01-10 14:24:17 +00:00
Mark Dykes 45503af4ce Merge "smccc: add get smc function id num macro" into integration 2020-01-09 20:22:16 +00:00
Manish Pandey 1f4b717051 Merge "Simplify PMF helper macro definitions across header files" into integration 2020-01-09 17:38:03 +00:00
Manish Pandey 1ab2dc1a55 Merge "Remove redundant declarations." into integration 2020-01-09 17:34:49 +00:00
Alexei Fedorov 6e94d56a67 Merge "Tegra194: mce: fix error code signedness" into integration 2020-01-09 15:26:47 +00:00
Olivier Deprez e073e0700e smccc: add get smc function id num macro
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2953f0a6f35bc678402bc185640d1f328b065af5
2020-01-09 12:14:14 +01:00
Olivier Deprez f1f7201994 plat: nvidia: remove spurious UTF-8 characters at top of platform files
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423
2020-01-09 10:51:25 +01:00
Madhukar Pappireddy daa9b6ea64 Simplify PMF helper macro definitions across header files
In further patches, we aim to enable -Wredundant-decls by default.
This rearragement of helper macros is necessary to make Coverity
tool happy as well as making sure there are no redundant function
declarations for PMF related declarations.

Also, PMF related macros were added to provide appropriate function
declarations for helper APIs which capture PSCI statistics.

Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-08 18:00:34 -06:00
Madhukar Pappireddy 7a05f06a84 Remove redundant declarations.
In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-08 18:00:25 -06:00
laurenw-arm 3c0d784cfb docs: Creating a Change Log Template File
Creating a Change Log Template for ALL to update with relevant
new features, changes, fixes and known issues for each upcoming
release of Trusted Firmware-A.

The contents of this file should be added to the collective change log
at the time of release code freeze.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Idfbdcef0d40b10312dc88b6e1cbe31856fda887e
2020-01-08 15:52:10 -06:00
Mark Dykes 650a435c83 Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"
This reverts commit de9bf1d8a2.

Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f
2020-01-08 20:37:18 +00:00
Varun Wadekar e1fcb1bf89 Tegra194: mce: fix error code signedness
The MCE driver's helper functions were using postive values as error
codes.

This patch updates the functions to return negative values as error
codes instead. Some functions are updated to use the right error code.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6
2020-01-08 09:19:05 -08:00