Commit Graph

5194 Commits

Author SHA1 Message Date
Dave Gerlach a9f46fad82 feat(ti): allow build config of low power mode support
Not all K3 platforms support low power mode, so to allow these
features to be included for platforms that do in build and
therefore reported in the PSCI caps, define K3_PM_SYSTEM_SUSPEND
flag that can be set during build that will cause appropriate
space and functionality to be included in build for system
suspend support.

Change-Id: I821fbbd5232d91de6c40f63254b855e285d9b3e8
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-27 12:06:53 -05:00
Dave Gerlach 38164e64bd feat(ti): increase SEC_SRAM_SIZE to 128k
Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-27 12:06:53 -05:00
Dave Gerlach 2393c27680 feat(ti): add PSCI handlers for system suspend
Add necessary K3 PSCI handlers to enable system suspend to be reported
in the PSCI capabilities when asked during OS boot.

Additionally, have the handlers provide information that all domains
should be off and also have the power domain suspend handler invoke the
TISCI_MSG_ENTER_SLEEP message to enter system suspend.

Change-Id: I351a16167770e9909e8ca525ee0d74fa93331194
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-27 12:06:53 -05:00
Dave Gerlach b40a467783 feat(ti): add gic save and restore calls
Add functions to save and restore GICv3 redist and dist contexts during
low power mode and then call these during the suspend entry and finish
psci handlers.

Change-Id: I26c2c0f3b7fc925de3b349499fa42d2405441577
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-27 12:06:53 -05:00
Dave Gerlach cf5868b8cd feat(ti): add enter sleep method
This TISCI API must be used to trigger entry into system suspend, and
this is done through the use of TI_SCI_MSG_ENTER_SLEEP. Introduce a
method to send this message.

Change-Id: Id7af5fb2a34623ad69e76764f389ff4d8d259fba
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2022-04-27 12:06:53 -05:00
Madhukar Pappireddy 3dbbd41f39 Merge changes Ibe6fd206,Icdca3de6,I72016620,I57a2787c into integration
* changes:
  fix(versal): fix coverity scan warnings
  feat(versal): get version for ATF related EEMI APIs
  feat(versal): enhance PM_IOCTL EEMI API to support additional arg
  feat(versal): add common interfaces to handle EEMI commands
2022-04-27 16:40:38 +02:00
Manish Pandey 9284d2129e Merge "refactor(twed): improve TWED enablement in EL-3" into integration 2022-04-27 11:01:52 +02:00
Tanmay Shah 0b15187225 fix(versal): fix coverity scan warnings
- Fix memory overrun issue
- include header file to fix Unknown macro warning

Change-Id: Ibe6fd206f44fbc22de746d255ff17c2b2325cd7b
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-04-27 01:44:20 +02:00
Ronak Jain da6e654bc8 feat(versal): get version for ATF related EEMI APIs
The patch does below things.

1. As per current implementation, when Linux send a request to ATF to
 get the version of APIs which are implemented in ATF then ATF wasn't
 returning any version because there is a check for LIBPM module id.
 The ATF is used to return version for the APIs which are implemented
 in the firmware only.

 Hence moved this switch-case before checking module id to get ATF
 version.

 Also, no need to pass Linux request to the firmware for the APIs
 which are implemented in ATF instead return success after updating
 version.

2. As per current implementation, higher 16-bit is used for ATF
 version and lower 16-bit is used for firmware version. Now, removed
 16-bit shift operation and send complete word i.e. 32-bit to Linux
 user as there is no user who checks ATF version.

3. Add bit mask support in the feature check PM EEMI API for QUERY and
 IOCTL ids.

Change-Id: Icdca3de6659f3b673b81a423ed79a3c20b678768
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-04-27 01:44:11 +02:00
Venkatesh Yadav Abbarapu d34a5db8a7 feat(versal): enhance PM_IOCTL EEMI API to support additional arg
Currently, SMC handler is limited to parsing 5 arguments (1 API ID + 4
32-bit command args). Extend this handling to support one more 32-bit
command argument which is necessary to support new IOCTL IDs for
secure read/write interface.

Note that, this change is completely transparent and does not affect
existing functionality of any of the EEMI APIs.

Change-Id: I72016620eeeaf598f14853512120bfb30bb9a3e9
Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-04-27 01:44:02 +02:00
Tanmay Shah 1397967490 feat(versal): add common interfaces to handle EEMI commands
This change adds common interfaces to handle commands from firmware driver
to power management controller. It removes big chunk of source line of code
that was handling each command separately and doing same repetitive work.

EEMI - Embedded Energy Management Interface is Xilinx proprietary
protocol to allow communication between power management controller
and different processing clusters.

As of now, Each EEMI command has its own implementation in TF-A.
This is redundant. Essentially most EEMI command implementation
in TF-A  does same work. It prepares payload received from kernel, sends
payload to firmware, receives response from firmware and send response
back to kernel.

The same functionality can be achieved if common interface is used among
multiple EEMI commands. This change divides platform management related
SMCCC requests into 4 categories.

1) EEMI commands required for backward compatibility.

Some EEMI commands are still required for backward compatibility
until removed completely or its use is changed to accommodate
common interface

2) EEMI commands that require for PSCI interface and accessed from debugfs

For example EEMI calls related to CPU suspend/resume

3) TF-A specific requests

Functionality such as getting TF-A version and getting callback
data for platform management is handled by this interface

4) Common interface for rest of EEMI commands

This handlers performs payload and firmware response transaction job for
rest of EEMI commands. Also it parses module ID from SMC payload and inserts
in IPI request. If not module ID is found, then default is LIBPM_MODULE_ID.
This helps in making common path in TF-A for all the modules in PLM firmware

Change-Id: I57a2787c7fff9f2e1d1f9003b3daab092632d57e
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
2022-04-27 01:43:41 +02:00
Madhukar Pappireddy b08a199b40 Merge "fix(xilinx): fix mismatching function prototype" into integration 2022-04-26 04:45:16 +02:00
Lauren Wehrmeister 394f2ea034 Merge changes Iccfa7ec6,Ide9a7af4 into integration
* changes:
  feat(intel): add macro to switch between different UART PORT
  feat(intel): add SMC support for ROM Patch SHA384 mailbox
2022-04-25 23:02:07 +02:00
Madhukar Pappireddy 5b44657a97 Merge changes from topic "st_fwu_bkp_reg" into integration
* changes:
  feat(stm32mp1): retry 3 times FWU trial boot
  refactor(stm32mp1): update backup reg for FWU
2022-04-25 19:28:33 +02:00
Yann Gautier 429f10e336 fix(stm32mp1): correct dtc version check
Depending on the shell used, the grep command can fail, leading to
a wrong dtc version detection. Correct that by adding quotes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I329ec929559c94bf1bf99b127662c9d978e067cf
2022-04-22 13:23:22 +02:00
Manish Pandey dfc59a7b82 Merge changes from topic "st_nvmem_layout" into integration
* changes:
  refactor(stm32mp1-fdts): remove nvmem_layout node
  refactor(stm32mp1): drop the "st,stm32-nvmem-layout" node
  refactor(st): remove useless includes
2022-04-19 16:11:24 +02:00
Jayanth Dodderi Chidanand 781d07a421 refactor(twed): improve TWED enablement in EL-3
The current implementation uses plat_arm API under generic code.
"plat_arm" API is a convention used with Arm common platform layer
and is reserved for that purpose. In addition, the function has a
weak definition which is not encouraged in TF-A.

Henceforth, removing the weak API with a configurable macro "TWED_DELAY"
of numeric data type in generic code and simplifying the implementation.
By default "TWED_DELAY" is defined to zero, and the delay value need to
be explicitly set by the platforms during buildtime.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I25cd6f628e863dc40415ced3a82d0662fdf2d75a
2022-04-17 23:48:10 +01:00
Zelalem Aweke 8b95e84870 refactor(context mgmt): add cm_prepare_el3_exit_ns function
As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' function. The function is
a wrapper to 'cm_prepare_el3_exit' function for Non-secure state.

When EL2 sysregs context exists (CTX_INCLUDE_EL2_REGS is
enabled) EL1 and EL2 sysreg values are restored from the context
instead of directly updating the registers.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9b071030576bb05500d54090e2a03b3f125d1653
2022-04-12 17:42:11 +02:00
Sandrine Bailleux 2d1ba79cde Merge "style(plat/arm/corstone1000): resolve checkpatch warnings" into integration 2022-04-12 17:17:14 +02:00
Manish V Badarkhe def5571db2 refactor(arm): use MBEDTLS_CONFIG_FILE macro
Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3ab1e69481b2c37a6f7455a106b6e
2022-04-11 14:32:59 +02:00
Sandrine Bailleux a934332d98 Merge "refactor(corstone700): namespace MHU driver filenames" into integration 2022-04-11 12:47:08 +02:00
Venkatesh Yadav Abbarapu 81333eac71 fix(xilinx): fix mismatching function prototype
The reported function raises a error when compilers assert the flag
`-Warray-parameter=`, signaling that an array-type argument was promoted
to a pointer-type argument. We observed this behaviour with the gcc 11.2
version.

plat/xilinx/common/pm_service/pm_ipi.c:263:34: error: argument 1 of type 'uint32_t *'
{aka 'unsigned int *'} declared as a pointer [-Werror=array-parameter=]
263 | uint32_t calculate_crc(uint32_t *payload, uint32_t bufsize)
      |                        ~~~~~~~~~~^~~~~~~
In file included from plat/xilinx/common/pm_service/pm_ipi.c:16:
plat/xilinx/common/include/pm_ipi.h:30:33: note: previously declared as an array 'uint32_t[8]'
{aka 'unsigned int[8]'}
   30 | uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize);
      |                        ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
cc1.real: all warnings being treated as errors

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I7329f2e76ee0ca5faba71eb50babd20a796fee64
2022-04-11 09:27:02 +05:30
Yann Gautier 03d20776ef fix(st): remove extra chars from dtc version
In some implementations of dtc tool (e.g. with yocto), there can be a 'v'
at the beginning of the version, and a '+' at the end. Just keep numbers
then, with a grep -o.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I180e97ab75ba3e5ceacb4b1961a1f22788b428a3
2022-04-05 08:58:16 +02:00
Boon Khai Ng 447e699f70 feat(intel): add macro to switch between different UART PORT
HSD #1509626040:
This patch is to add the flexibility for BL2 and BL31
to choose different UART output port at platform_def.h
using parameter PLAT_INTEL_UART_BASE

This patch also fixing the plat_helpers.S where the
UART BASE is hardcoded to PLAT_UART0_BASE. It is then
switched to CRASH_CONSOLE_BASE.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f
2022-04-05 14:25:30 +08:00
Sieu Mun Tang 77902fca8f feat(intel): add SMC support for ROM Patch SHA384 mailbox
HSD #16014059592:
Add support for ROM Patch SHA384 mailbox SMC call.

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ide9a7af41a089980745cb7216a9bf85e7fbd84e3
2022-04-05 14:23:26 +08:00
Sandrine Bailleux 510dc79c85 refactor(corstone700): namespace MHU driver filenames
There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.

In preparation for this, rename the Corstone-700 MHU driver source
files and prefix them with the name of the platform to avoid any
ambiguity or name clashes with the upcoming generic MHU driver. Also
rename the header guard accordingly.

This renaming is inline with other platform-specific MHU drivers, such
as the ones used on Broadcom [1], Socionext [2] or Amlogic [3] platforms.

[1] plat/brcm/common/brcm_mhu.h
[2] plat/socionext/synquacer/drivers/mhu/sq_mhu.h
[3] plat/amlogic/common/aml_mhu.c

Change-Id: I8a5e5b16e7c19bf931a90422dfca8f6a2a0663b4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-04-01 10:16:01 +02:00
David Vincze 83b3ed260b style(plat/arm/corstone1000): resolve checkpatch warnings
Change-Id: Ic8cb9b0834806675c792018e809d7ba77fbe856f
Signed-off-by: David Vincze <david.vincze@arm.com>
2022-03-31 10:59:41 +02:00
Nicolas Toromanoff f87de907c8 feat(stm32mp1): retry 3 times FWU trial boot
If we reboot 3 times in trial mode, BL2 will select previous boot image.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Change-Id: I82b423cc84f0471fdb6fa7c393fc5fe411d25c06
2022-03-30 15:44:40 +02:00
Yann Gautier e633f9c52f refactor(stm32mp1): update backup reg for FWU
Change the backup register used to store FWU parameters from 21 to 10.
This is chosen to have a Read/Write secure and Read non-secure register.
The mapping is also changed: only the first 4 bits will be used to store
the FWU index. The 4 next bits will be used to store count info. The
other bits are reserved.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Change-Id: I9249768287ec5688ba2d8711ce04d429763543d7
2022-03-30 13:34:59 +02:00
Jiafei Pan 5161cfde9b fix(layerscape): fix coverity issue
Check return value of mmap_add_dynamic_region().

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I84e257b3052371e18af158c3254f42a1bae0da10
2022-03-30 10:38:22 +08:00
Soby Mathew ad88c37080 Merge changes from topic "rme-attest" into integration
* changes:
  feat(rme): add dummy realm attestation key to RMMD
  feat(rme): add dummy platform token to RMMD
2022-03-28 18:32:27 +02:00
Patrick Delaunay c5bf1b0971 refactor(stm32mp1): drop the "st,stm32-nvmem-layout" node
Simplify the DT parsing by removing the parsing of the nvmem layout node
with "st,stm32-nvmem-layout" compatible.

The expected OTP NAME can directly be found in a sub-node named
NAME@ADDRESS of the BSEC node, the NVMEM provider node.

This patch also removes this specific binding introduced for TF-A.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic703385fad1bec5bef1cee583fbe9fbbf6aea216
2022-03-28 18:29:59 +02:00
Yann Gautier b9a6dbc1ba refactor(st): remove useless includes
The stm32mp_dt.c file does not need anything from DDR header files.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibfe23204d68ee2e863cd2eda3d725baa830b729a
2022-03-28 18:29:59 +02:00
Soby Mathew a0435105f2 feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
parameters:
    * Fid (0xC400001B2).
    * Attestation key buffer PA (the realm attestation key is copied
      at this address by the monitor).
    * Attestation key buffer length as input and size of realm
      attesation key as output.
    * Type of elliptic curve.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I12d8d98fd221f4638ef225c9383374ddf6e65eac
2022-03-28 15:02:01 +02:00
Jiafei Pan 0b0e676698 feat(ls1088aqds): add ls1088aqds board support
Add QDS support for ls1088a.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6c7a7a23fa6b9ba01c011a7e6237f8063d45e261
2022-03-27 23:24:24 +08:00
Jiafei Pan 2771dd0293 feat(ls1088ardb): add ls1088ardb board support
The LS1088A reference design board provides a comprehensive platform
that enables design and evaluation of the product (LS1088A processor).

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If4ca24fcee7a4c2c514303853955f1b00298c0e5
2022-03-27 23:24:24 +08:00
Jiafei Pan 9df5ba05b4 feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated
SoC device featuring eight extremely power-efficient 64-bit ARM
Cortex-A53 cores with ECC-protected L1 and L2 cache memories for
high reliability, running up to 1.6 GHz.

This patch is to add ls1088a SoC support in TF-A.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
2022-03-27 23:24:24 +08:00
Biwen Li ceae374357 refactor(layerscape): refine comparison of inerconnection
Refine the code to be compatible with new CCN504 which is used
by ls2088a.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2e2b3bbb9392862b04bf8a89dfb9575bf4be974a
2022-03-27 23:24:24 +08:00
Jiafei Pan 602cf53b6f feat(layerscape): add soc helper macro definition for chassis 3
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I27b3a1f597de84dc2a007798e54eb919c877281a
2022-03-27 23:24:24 +08:00
Biwen Li 9550ce9ddd feat(layerscape): add CHASSIS 3 support for tbbr
Support CHASSIS 3.0(such as SoC LS1088A).

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I60843bc4d604f0de1d91c6d3ad5eb4921cdcc91a
2022-03-27 23:24:24 +08:00
Jiafei Pan 0d396d6455 feat(layerscape): define more chassis 3 hardware address
Add base address definiton for Chassis 3 platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6041b93c9e9bb49af60743bd277ac7cc6f1b9da8
2022-03-27 23:24:24 +08:00
Jiafei Pan cd960f5009 feat(lx2): enable DDR erratas for lx2 platforms
Enable DDR erratas for lx2 platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia2cf6ed077acf81882247153ec38bda708a6f007
2022-03-27 23:24:24 +08:00
Jiafei Pan 3412716b30 feat(layerscape): print DDR errata information
Print Errata information in debug mode.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I70d6baa4dc3ffd79fedbc827555268d8f06605c7
2022-03-27 23:24:24 +08:00
Pankit Garg 291adf521a feat(nxp-ddr): add workaround for errata A050958
Set the receiver gain to max value to recover
cold temp marginality issue for phy-gen2

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If639fa3ed404cf6e1b8abcc2b7137db1fdd0b2c2
2022-03-27 23:24:24 +08:00
Jiafei Pan 85bd092943 feat(layerscape): add new soc errata a010539 support
Add new soc errata a010539 support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Idbd8caaac12da8ab4f39dc0019cb656bcf4f3401
2022-03-27 23:24:24 +08:00
Jiafei Pan 785ee93cc3 feat(layerscape): add new soc errata a009660 support
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ice37155d971dec5c610026043e34b64f761fc1b7
2022-03-27 23:24:24 +08:00
Biwen Li e2818d0afc fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
Fix build issue of mmap_add_ddr_region_dynamically():
ls_bl2_el3_setup.c:(.text.bl2_plat_preload_setup+0x28): undefined
reference to mmap_add_ddr_region_dynamically

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I74a8b4c2337fc0646d6acb16ce61755c5efbdf38
2022-03-27 23:24:24 +08:00
Soby Mathew 0f9159b7eb feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
    * Fid (0xC40001B3).
    * Platform token PA (the platform token is copied at this address by
      the monitor). The challenge object needs to be passed by
      the caller in this buffer.
    * Platform token len.
    * Challenge object len.

When calling the SMC, the platform token buffer received by EL3 contains
the challenge object. It is not used on the FVP and is only printed to
the log.

Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I8b2f1d54426c04e76d7a3baa6b0fbc40b0116348
2022-03-25 17:12:26 +00:00
Manish Pandey 91e52cf0ca Merge "fix(tegra194/ras): remove incorrect erxctlr assert" into integration 2022-03-22 23:02:24 +01:00
Manish Pandey 2ff6a49ea6 Merge changes from topic "stm32mp13" into integration
* changes:
  feat(stm32mp1): select platform compilation either by flag or DT
  feat(stm32mp1-fdts): add support for STM32MP13 DK board
  feat(stm32mp1-fdts): add DDR support for STM32MP13
  feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
  feat(stm32mp1): updates for STM32MP13 device tree compilation
  feat(stm32mp1-fdts): add DT files for STM32MP13
  feat(dt-bindings): add TZC400 bindings for STM32MP13
  feat(stm32mp1): add "Boot mode" management for STM32MP13
  feat(stm32mp1): manage HSLV on STM32MP13
  feat(stm32mp1): add sdmmc compatible in platform define
  feat(st-sdmmc2): allow compatible to be defined in platform code
  feat(stm32mp1): update IO compensation on STM32MP13
  feat(stm32mp1): call pmic_voltages_init() in platform init
  feat(st-pmic): add pmic_voltages_init() function
  feat(stm32mp1): update CFG0 OTP for STM32MP13
  feat(stm32mp1): usb descriptor update for STM32MP13
  feat(st-clock): add clock driver for STM32MP13
  feat(dt-bindings): add bindings for STM32MP13
  feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
  feat(stm32mp1): use only one filter for TZC400 on STM32MP13
  feat(stm32mp1): add a second fixed regulator
  feat(stm32mp1): adaptations for STM32MP13 image header
  feat(stm32mp1): update boot API for header v2.0
  feat(stm32mp1): update IP addresses for STM32MP13
  feat(stm32mp1): add part numbers for STM32MP13
  feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
  feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
  feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
  feat(stm32mp1): remove unsupported features on STM32MP13
  feat(stm32mp1): update memory mapping for STM32MP13
  feat(stm32mp1): introduce new flag for STM32MP13
  feat(st): update stm32image tool for header v2
2022-03-22 16:42:16 +01:00