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9 Commits

Author SHA1 Message Date
Hadi Asyrafi fea24b88e4 intel: stratix10: Fix reliance on hard coded clock information 
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
 2019-08-13 18:20:53 +08:00
Hadi Asyrafi 3f7b1490dc intel: Platform common code refactor 
Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
 2019-08-07 12:19:11 +00:00
Soby Mathew d0d0f17164 Merge changes from topic "jc/shift-overflow" into integration 
* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour
 2019-07-16 10:11:27 +00:00
Justin Chadwell 36cfbf3ca2 Update intel platform to not rely on undefined overflow behaviour 
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
 2019-07-11 12:10:58 +01:00
Tien Hock, Loh 0943ea379f plat/intel: Fix SMPLSEL for MMC 
MMC sample select needs to be set properly so that DWMMC clock can be
driven to 50Mhz

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a
 2019-07-10 11:39:03 +08:00
Muhammad Hadi Asyrafi Abdul Halim 10e70f87e0 intel: Enable watchdog timer on Intel S10 platform 
Watchdog driver support & enablement during platform setup

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
 2019-03-21 10:35:24 +08:00
Tien Hock, Loh 1cf55aba49 plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform 
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-26 09:25:14 +08:00
Loh Tien Hock 51f366ac85 plat: intel: Fix faulty DDR calibration value 
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-13 14:39:31 +08:00
Loh Tien Hock 9d82ef26c6 plat: intel: Add BL2 support for Stratix 10 SoC 
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
 2019-02-04 16:17:24 +08:00