Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, which is 1
by default, but overridden by bl1.ld.S. Currently, ALIGN(16)
of the .data section is redundant because commit 4128659076
("Fix boot failures on some builds linked with ld.lld.") padded
out the previous section to work around the issue of LLD version
<= 10.0. This will be fixed in the future release of LLVM, so
I am keeping the proper way to align LMA.
[2] bl1.ld.S and bl2_el3.ld.S define __DATA_RAM_{START,END}__ instead
of __DATA_{START,END}__. I put them out of the .data section.
[3] SORT_BY_ALIGNMENT() is missing tsp.ld.S, sp_min.ld.S, and
mediatek/mt6795/bl31.ld.S. This commit adds SORT_BY_ALIGNMENT()
for all images, so the symbol order in those three will change,
but I do not think it is a big deal.
Change-Id: I215bb23c319f045cd88e6f4e8ee2518c67f03692
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The stacks section is the same for all BL linker scripts.
Move it to the common header file.
Change-Id: Ibd253488667ab4f69702d56ff9e9929376704f6c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Only BL1 specifies '.' in the address field of the stacks section.
Commit 4f59d8359f ("Make BL1 RO and RW base addresses configurable")
added '.' on purpose but the commit message does not help to understand
why.
This commit gets rid of it in order to factor out the stacks section
into include/common/bl_common.ld.h
I compared the build result for PLAT=qemu.
'aarch64-linux-gnu-nm -n build/qemu/release/bl1/bl1.elf' will change
as follows:
@@ -336,8 +336,8 @@
000000000e04e0e0 d max_log_level
000000000e04e0e4 D console_state
000000000e04e0e5 D __DATA_RAM_END__
-000000000e04e0e5 B __STACKS_START__
000000000e04e100 b platform_normal_stacks
+000000000e04e100 B __STACKS_START__
000000000e04f100 b bl1_cpu_context
000000000e04f100 B __BSS_START__
000000000e04f100 B __STACKS_END__
After this change, __STACKS_START__ will match to platform_normal_stacks,
and I think it makes more sense.
'aarch64-linux-gnu-objdump -h build/qemu/release/bl1/bl1.elf' will change
as follows:
@@ -9,11 +9,11 @@
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .data 000000e5 000000000e04e000 0000000000004a60 0001e000 2**4
CONTENTS, ALLOC, LOAD, DATA
- 3 stacks 0000101b 000000000e04e0e5 000000000e04e0e5 0001e0e5 2**6
+ 3 stacks 00001000 000000000e04e100 0000000000004b45 0001e100 2**6
ALLOC
- 4 .bss 000007e0 000000000e04f100 000000000e04f100 0001e0e5 2**5
+ 4 .bss 000007e0 000000000e04f100 0000000000004b50 0001f100 2**5
ALLOC
- 5 xlat_table 00006000 000000000e050000 000000000e050000 0001e0e5 2**12
+ 5 xlat_table 00006000 000000000e050000 0000000000004b45 00020000 2**12
ALLOC
6 coherent_ram 00000000 000000000e056000 000000000e056000 0001f000 2**12
CONTENTS
Sandrine pointed me to a useful document [1] to understand why LMAs of
stacks, .bss, and xlat_table section have changed.
Before this patch, they fell into this scenario:
"If the section has a specific VMA address, then this is used as the
LMA address as well."
With this commit, the following applies:
"Otherwise if a memory region can be found that is compatible with the
current section, and this region contains at least one section, then
the LMA is set so the difference between the VMA and LMA is the same
as the difference between the VMA and LMA of the last section in the
located region."
Anyway, those three sections are not loaded, so the LMA changes will not
be a problem. The size of bl1.bin is still the same.
QEMU still boots successfully with this change.
A good thing is, this fixes the error for the latest LLD. If I use the
mainline LLVM, I see the following error. The alignment check will probably
be included in the LLVM 11 release, so it is better to fix it now.
$ PLAT=qemu CC=clang CROSS_COMPILE=aarch64-linux-gnu-
[ snip ]
ld.lld: error: address (0xe04e0e5) of section stacks is not a multiple of alignment (64)
make: *** [Makefile:1050: build/qemu/release/bl1/bl1.elf] Error 1
[1]: https://sourceware.org/binutils/docs/ld/Output-Section-LMA.html#Output-Section-LMA
Change-Id: I3d2f3cc2858be8b3ce2eab3812a76d1e0b5f3a32
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
'make doc' will now fail if Sphinx outputs any warning messages during
documentation generation.
Change-Id: I3e466af58ccf29b14a7e61037539b79ab6fc6037
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This commit fixes an assertion that was triggering in certain contexts:
ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790
Change-Id: Ia55b3fb4f496c8cd791ea6093d122edae0a7e92a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This is a fixup for patch 3ba55a3c5f
("docs: Update SMCCC doc, other changes for release"), where some
links names got changed but their references didn't.
Change-Id: I980d04dde338f3539a2ec1ae2e807440587b1cf5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Following the messages on the mailing list regarding the possible issue around
reading DTB's information, we decided to flag the fconf feature as experimental.
A uniform approach should be used to handle properties miss and DTB validation.
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: Ib3c86e81fb2e89452c593f68d825d3d8f505e1fb
Updating the change log for the v2.3 release and the upcoming change log
template for v2.4 release.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ice875d3c93227069738a429d4b945512af8470e9
A small set of misc changes to ensure correctness before the v2.3
release.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I5b4e35b3b46616df0453cecff61f5a414951cd62
- Include the platform documentation in the table of contents.
- Add a title for the document. Without this, the platform
documentation was listed under a 'Description' title on page
https://trustedfirmware-a.readthedocs.io/en/latest/plat/index.html
- Change TF-A git repository URL to point to tf.org (rather than the
deprecated read-only mirror on Github).
- Fix the restructuredText syntax for the FIP command line. It was
not displayed at all on the rendered version.
Change-Id: I7a0f062bcf8e0dfc65e8f8bdd6775c497a47e619
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional mmap entries are required to map the shared SRAM and
the IO regions. A corresponding number of additional translation
tables are required as well.
Change-Id: I1332a1305f2af62181387cf36954f6fb0e6f11ed
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
The arm_fpga platform code contains an dubious line to initialise some
timer. On closer inspection this turn out to be bogus, as this was only
needed on some special (older) FPGA board, and is actually not needed on
the current model. Also the base address was wrong anyways.
Remove the code entirely.
Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
To support compatibility with previous GICv3 driver version
this patch:
- restores original API for gicr_read_ipriority() and
gicr_wrtite_ipriority() functions;
- adds accessor functions for GICR_XXX0,1 registers, e.g.
GICR_IGROUPR0, GICR_ICFGR0, GICR_ICFGR1, etc.
Change-Id: I796a312a61665ff384e3d9de2f4b3c60f700b43b
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
RD-Daniel uses GIC-Clayton as its interrupt controller which is an
implementation of GICv4.1 architecture. Hence for RD-Daniel, enable
GICv4 extension support.
Change-Id: I45ae8c82376f8fe8fc0666306822ae2db74e71b8
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
GIC-Clayton supports multichip operation mode which allows it to connect
upto 16 other GIC-Clayton instances. GIC-Clayton's multichip programming
and operation remains same as GIC-600 with a minor change in the
SPI_BLOCKS and SPI_BLOCK_MIN shifts to accommodate additional SPI
ranges. So identify if the GIC v4 extension is enabled by the platform
makefile and appropriately select the SPI_BLOCKS and SPI_BLOCK_MIN
shifts.
Change-Id: I95fd80ef16af6c7ca09e2335539187b133052d41
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
This patch adds support for GICv4 extension for FVP platform.
Change-Id: Ia389b61266af669b1ca9b999a8b76476cab214f4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch adds support for GICv4 extension.
New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile
was added, and enables GICv4 related changes when set to 1.
This option defaults to 0.
Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch adds code to parse memory range information passed by
coreboot, and a simple helper to test whether a specific address belongs
to a range. This may be useful for coreboot-using platforms that need to
know information about the system's memory layout (e.g. to check whether
an address passed in via SMC targets valid DRAM).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
Increased the maximum size of BL2 image in order to
accommodate the BL2 image when TF-A build with no compiler
optimization for ARM platform.
Note: As of now, "no compiler optimization" build works
only when TRUSTED_BOOT_BOARD option is set to 0.
This change is verified using below CI configuration:
1. juno-no-optimize-default:juno-linux.uboot
2. fvp-no-optimize-default,fvp-default:fvp-tftf-fip.tftf-aemv8a-debug
Change-Id: I5932621237f8acd1b510682388f3ba78eae90ea4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3)
to check whether the dcache is enabled.
Using is_dcache_enabled() is cleaner, and a good abstraction for
the library code like this.
A problem is is_dcache_enabled() is declared in the local header,
lib/xlat_tables_v2/xlat_tables_private.h
I searched for a good place to declare this helper. Moving it to
arch_helpers.h, closed to cache operation helpers, looks good enough
to me.
I also changed the type of 'is_cached' to bool for consistency,
and to avoid MISRA warnings.
Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch provides support for GICv3.1 extended PPI and SPI
range. The option is enabled by setting to 1 and passing
`GIC_EXT_INTID` build flag to gicv3.mk makefile.
This option defaults to 0 with no extended range support.
Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Default board configuration was set to bcm958742k which is not present
in current codebase. This causes a default platform build to fail.
Changing to bcm958742t.
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ie24f94ef0ef316ff56fe142df5de45d70ba93c28
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.
Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>
with commit a6ea06f5, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fpga platform.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic5ccae842b39b7db06d4f23c5738b174c42edf63
Masahiro Yamada
Sandrine Bailleux
Mark Dykes
Madhukar Pappireddy
Chris Kay
Louis Mayencourt
laurenw-arm
joanna.farley
Manish Pandey
Aditya Angadi
Sheetal Tigadoli
Andre Przywara
Alexei Fedorov
Vijayenthiran Subramaniam
Olivier Deprez
Julius Werner
Manish V Badarkhe
Max Shvetsov
John Powell