This patch adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: Ic691ab909bc671d8f0f43ffc443f46237c75536d
This patch programs the CNTCTLBase.CNTNSAR to give non-secure access
to timer frame 1. It also programs the CNTCTLBase.CNTACR1 to give
access to all the timer registers in this frame.
Change-Id: Ia10c9572a70bd5910031de1994116bb9314efd80
Conflicts:
plat/juno/bl31_plat_setup.c
plat/juno/platform.h
This patch adds support for the PSCI cpu_suspend api to allow entry
into low power states until affinity level 1 i.e. cluster. It mainly
ensures that a consolidated power off command which specifies the
level to which each affinity level should be powered down is sent to
the SCP. It also ensures the MHU driver waits for the SCP to pick up a
command before doing further processing.
Change-Id: I8ad10652d388525730a228f0900a659246dd5087
This patch ensures that workarounds for erratas #806969, #813420 & #814670 that
affect Cortex-A57 r0p0 as described in the errata notice document are
implemented after every reset on each cpu.
Change-Id: I37ee16bafa623c405197925c5a0e66811d4c50ae
Before attempting to write a character, the PL011 driver polls
the PL011_UARTFR_TXFF bit to know whether the UART FIFO is full.
However, the comparison with 1 was incorrect because
PL011_UARTFR_TXFF is not at bit 0. This patch fixes it.
Change-Id: I4b53c28612f58581c6189ed6c794ed02cc2a89e3
Enabling BL3-1 entrypoint as the CPU reset vector in place of the
BL1 entrypoint is not supported on Juno at the moment. This patch
modifies the build system so that the build will crash straight
away if the user attempts to use this feature on Juno.
Change-Id: I641275fa37c2892fae7b944219b406f945e7e1b4
This concerns only debug builds. In BL2, we now pass a special value
to BL3-1 through x1. In BL3-1, we check that we receive the correct
value. This ensures that any platform set value is correctly passed
from BL2 to BL3-1.
Change-Id: Icb94d0e99ca445dcbe574a7d5e291659bba2209e
Juno code can re-use the enable_mmu_elX() functions from
lib/aarch64/xlat_tables.c.
Because the Juno port now includes plat/common/aarch64/plat_common.c
the juno specific 'plat_common.c' needs to be renamed to avoid
name conflicts at build time.
Change-Id: I1e9cc6484643fbf516dfac0236573e0474ccc0a2
On Juno, BL3-1 arguments used to sit at the beginning of the normal
DRAM. This patch moves them in trusted RAM. BL2 now allocates them
as a platform-specific static variable. BL3-1 then copies them
internally before the MMU is enabled.
Change-Id: I5cf526edfab5b49925b685092ff78506a5882f49
The BL3-0 gets loaded by BL2 but it will never be executed by the AP.
Therefore we don't care about the entry point information returned
by load_image() function.
Change-Id: I9bf7e04fa41a205b7595f58f0c3484a2507141fc
There are cases where the entry point information is useless to the
caller, e.g. when an image just needs to be loaded in memory but won't
ever be executed.
This patch allows load_image() function to take a NULL pointer as the
entry point parameter. In this case, it won't be populated.
Change-Id: Ie9394b054457706c6699926c5e0206e0c3851c56
This reverts commit 033c52bc054b730bdeacba1cc90c38efc8c3a131
because the workaround it introduced is no longer needed since
BL3-1 interface rework.
This does not revert the change on BL33 base address on Juno, though.
Change-Id: Idc747718a0af94c54931d4a9932f145350b0a75f
The interface to load an image has changed so load_bl30() function
needs to be modified accordingly.
Change-Id: I7ff3f808579f6dcd4ddab7aa17f18932152ea33f
The platform_mem_init() function doesn't do anything on Juno.
We don't need to carry out any memory initialization as the
Secure RAM is accessible straight away.
Change-Id: Ic5f778a71279add95a75c20d0f7b2cf57968c5df
At present BL3-1 has access to all of the SRAM, including
regions that are mapped as read-only and non-cacheable by other
firmware images.
This patch restricts BL3-1 to only be able to read/write from
memory used for its own data sections
Change-Id: I32126adaa93d8e42f4cea5a8f676b3efe3eb04f6
Propagate FVP changes introduced by these 3 commits:
- 29fb905d5f Rework handover interface between BL stages
- 4112bfa0c2 Populate BL31 input parameters as per new spec
- 6871c5d3a2 Rework memory information passing to BL3-x images
Change-Id: If024f575782d9c74db4cf929a2ab40563921dedd
Instead of having a single version of the MMU setup functions for all
bootloader images that can execute either in EL3 or in EL1, provide
separate functions for EL1 and EL3. Each bootloader image can then
call the appropriate version of these functions. The aim is to reduce
the amount of code compiled in each BL image by embedding only what's
needed (e.g. BL1 to embed only EL3 variants).
Change-Id: Ie3f6fb58f7d9ea4e4085b5069e27d6b9dceaa286
This patch implements the TSP on Juno. It executes from Secure RAM.
Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.
This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest slice
of the cake since they will most probably grow the most.
A few useful numbers for reference (valid at the time of this patch):
|-----------------------|-------------------------------
| image size (debug) | extra space for the future
--------|-----------------------|-------------------------------
BL1 R/W | 28 KB | 4 KB
BL2 | 48 KB | 4 KB
BL3-1 | 96 KB | 8 KB
BL3-2 | 56 KB | 8 KB
--------|-----------------------|-------------------------------
Total | 228 KB | 24 KB = 252 KB
--------|-----------------------|-------------------------------
Note: On Juno, although the Secure RAM is 256 KB, the first 4KB
are reserved for the AP/SCP mailboxes.
Change-Id: I999ec39589c45beabe1ecd772641623e58569a6e
Instead of using the read_mpidr() helper functions to read the
MPIDR_EL1 system register, assembler coded functions should
use MRS/MSR instructions. This results in faster and more
compact code.
Change-Id: I42bb61a926113c4f80aa1ce72ee29ab26cd8fa43
Add memory barriers to ensure that all translation table writes
have drained into memory, the TLB invalidation is complete,
and translation register writes are committed before enabling
the MMU.
Also ensure the MMU enable takes effect immediately.
These changes are necessary because of commit 8cec598ba3.
Change-Id: I65b5c3593af27f19da3fd2170c55f631f1ce7b81
disable_mmu() cannot work as a C function as there is no control
over data accesses generated by the compiler between disabling and
cleaning the data cache. This results in reading stale data from
main memory.
This patch removes the C version of this function in juno code.
An assembly version has been introduced in commit 2f5dcfef1d.
Change-Id: I0de10dbe2db8d22855bf1f60f1e48540a4861cb6
Because we needed to configure the trustzone controller on Juno,
minimal support for the TZC-400 had been added. However, a proper
TZC-400 driver has been introduced since then. This patch removes
the old, minimal header file and makes the necessary changes to use
the new one.
Change-Id: I4af1d8fb423e3214a0020c527bd2c1c2fcdb5c56
This is a miscellaneous commit that fixes all build
errors introduced by the rebase of the Juno codebase
on the latest trusted firmware.
- Make codebase consistent in its use of #include "" syntax
for user includes and #include <> syntax for system includes.
- Sort header files alphabetically
- Use tag names for structure types.
Replace instances of the former io_handle and io_dev_handle
types with uintptr_t.
- Review the .c and .S files for which header files really need
including and reorder the #include statements alphabetically.
Change-Id: I1d409fafb6dc257a38992ee15b22b0e890d040b0
This reverts commit ff7480a34839693fdba599f74e5c7e6e189eebb8.
because the architected timer is now initialised in architecture
code and no longer in platform code. See commit 9e86490f8f.
Change-Id: I0f12e006ba1574c7c0fc03c616503f33958b9596
As per commit bee8241711, remove all usage of the vpath keyword
in makefiles. Specify the relative paths to source files instead.
Also reorder source files in makefiles alphabetically.
Change-Id: Ic85c396f34e7a25a7239533f12bde3eed8da0ca2
Rename the array "mmap" in plat/juno/aarch64/plat_common.c to
"juno_mmap", to avoid confusion with the array of the same name
in lib/arch/aarch64/xlat_tables.c
Change-Id: If2f2976b1bc9177a14625a2a4559c32c5236090f
This extends the --gc-sections behaviour to the Juno-specific assembler
support functions in the firmware images by placing each function
into its own code section. This is achieved by using the 'func'
macro when declaring a function label.
Change-Id: I738370c0515face104531ab7944cc5bbdad49a9d
Ensure that each bootloader stage initializes the UART console
independently. As a result, both BL3-1 and BL2 platform code now
calls console_init() instead of relying on BL1 to perform console
setup.
Also perform the console initialisation earlier in BL1 because
it must be done before it is used e.g. through a printf() call
in an assert() statement.
Change-Id: I8bb58cf1f0e42a71a01abf65da30bfa4ae533665
Remove the hard coding of all the MMU related registers with 0 and
disable MMU by clearing the M and C bit in SCTLR_ELx.
Also remove use of partially qualified asm helper functions.
Change-Id: I383083f93a0a53143e58f146faf7755198f6a6ca
Enable Debug and SError exceptions:
- when receiving an SMC;
- when a CPU is physically powered up (upon resumption from suspend
or in response to a PSCI cpu_on call)
Change-Id: I7e5613e34034be6ed68ec9e2aef4de66aa5ac65e
The software running at a given exception level should handle
external aborts and SError interrupts itself.
Change-Id: Ic249fdf8472e0c64306ce3913562a2ac89c78627
Achin Gupta
Sandrine Bailleux