Commit Graph

1424 Commits

Author SHA1 Message Date
Chris Kay d97bade107 build(hooks): add commitlint hook
This change adds a configuration for commitlint - a tool designed to
enforce a particular commit message style - and run it as part of Git's
commit-msg hook. This validates commits immediately after the editor has
been exited, and the configuration is derived from the configuration we
provide to Commitizen.

While the configuration provided suggests a maximum header and body
length, neither of these are hard errors. This is to accommodate the
occasional commit where it may be difficult or impossible to comply
with the length requirements (for example, with a particularly long
scope, or a long URL in the message body).

Change-Id: Ib5e90472fd1f1da9c2bff47703c9682232ee5679
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-04-19 14:06:25 +01:00
Chris Kay ba39362f21 build(hooks): add Husky configuration
Husky is a tool for managing Git hooks within the repository itself.
Traditionally, commit hooks need to be manually installed on a per-user
basis, but Husky allows us to install these hooks either automatically
when `npm install` is invoked within the repository, or manually with
`npx husky install`.

This will become useful for us in the next few patches when we begin
introducing tools for enforcing a commit message style.

Change-Id: I64cae147e9ea910347416cfe0bcc4652ec9b4830
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-04-19 14:06:25 +01:00
Manish V Badarkhe 641c5ff69c docs: Update Mbed TLS supported version
Updated the documentation with latest Mbed TLS supported
version i.e. Mbed TLS v2.26.0

Fixes available in this version of Mbed TLS mainly affect
key generation/writing and certificates writing, which
are features used in the cert_create tool.

Release notes of Mbed TLSv2.26.0 are available here:
https://github.com/ARMmbed/mbedtls/releases/tag/v2.26.0

Change-Id: Ie15ee45d878b7681e15ec4bf64d54b416a31aa2f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-14 12:07:13 +01:00
Madhukar Pappireddy 511c7f3a9d Merge changes from topic "dcc_console" into integration
* changes:
  plat:xilinx:versal: Add JTAG DCC support
  plat:xilinx:zynqmp: Add JTAG DCC support
  drivers: dcc: Support JTAG DCC console
2021-04-13 21:42:55 +02:00
laurenw-arm a492edc49c lib/cpu: Workaround for Cortex A77 erratum 1946167
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.

SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
2021-04-06 10:20:55 -05:00
Venkatesh Yadav Abbarapu 0b25f4045a plat:xilinx:versal: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
2021-03-31 22:00:21 -06:00
Venkatesh Yadav Abbarapu c00baeecbb plat:xilinx:zynqmp: Add JTAG DCC support
As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
2021-03-31 22:00:04 -06:00
Venkatesh Yadav Abbarapu e5936205ae drivers: dcc: Support JTAG DCC console
The legacy console is gone. Re-add DCC console support based
on the multi-console framework.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
2021-03-31 21:59:45 -06:00
André Przywara 8078b5c5a0 Merge changes from topic "allwinner_h616" into integration
* changes:
  allwinner: H616: Add reserved-memory node to DT
  allwinner: Add Allwinner H616 SoC support
  allwinner: Add H616 SoC ID
  allwinner: Express memmap more dynamically
  allwinner: Move sunxi_cpu_power_off_self() into platforms
  allwinner: Move SEPARATE_NOBITS_REGION to platforms
  doc: allwinner: Reorder sections, document memory mapping
2021-03-30 16:21:13 +02:00
Andre Przywara 26123ca353 allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Andre Przywara fe90f9aecf doc: allwinner: Reorder sections, document memory mapping
Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installation.

Add some ASCII art about the layout of our virtual memory map, which
uses a non-trivial condensed virtual address space.

Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-25 15:25:54 +00:00
Manish Pandey 13d25345e7 doc: update maintainer list for Arm platforms
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I24a1697d0e0ec9289d272f0e96a252894faf12ef
2021-03-11 11:09:29 +00:00
Manish Pandey 32d440c77b doc: re-format maintainer.rst file rendering
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9fafeb966eeec35527647282b953d88f6aa383be
2021-03-11 11:01:18 +00:00
Mark Dykes 893716d7ff Merge "docs: Add GIC600AE FVP model version information" into integration 2021-03-03 21:30:17 +01:00
Manish V Badarkhe 051906bb2e docs: Add GIC600AE FVP model version information
Added GIC600AE FVP model version information.

Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-03-01 22:19:48 +00:00
johpow01 873d4241e3 Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0.  This patch enables support for this
feature in EL3 firmware.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
2021-02-25 22:01:59 +00:00
Yann Gautier f11279268b docs: stm32mp1: correct formatting issues
Add blank lines before lists and code example.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I901646e0be74227af983079d0cbe05c6a217fab6
2021-02-16 14:05:00 +01:00
Manish V Badarkhe d30a6615d1 doc: Build option to protect GICR frame
Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.

Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-02-09 15:54:19 +00:00
Jimmy Brisson 7dfb99118e Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.

Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-05 11:49:18 +00:00
Manish Pandey 477e28de58 Merge changes from topic "marvell-armada-docs" into integration
* changes:
  docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
  docs: marvell: Fix description of flash-image.bin image
  docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency
  docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board
  docs: marvell: Move Supported Marvell platforms to PLAT build option
2021-02-02 12:15:50 +00:00
Manish Pandey 6803d98945 Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
  plat: marvell: armada: a3k: Do not use 'echo -e' in Makefile
  docs: marvell: Update info about BOOTDEV=SATA
2021-02-02 11:17:54 +00:00
Manish Pandey 72645d5b60 Merge changes from topic "marvell-a3k-separate-flash-and-uart" into integration
* changes:
  docs: marvell: Update info about WTMI_IMG option
  plat: marvell: armada: a3k: Remove unused variable WTMI_SYSINIT_IMG from Makefile
  plat: marvell: armada: Show informative build messages and blank lines
  plat: marvell: armada: Move definition of mrvl_flash target to common marvell_common.mk file
  plat: marvell: armada: a3k: Use $(Q) instead of @
  plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
  plat: marvell: armada: a3k: Build UART image files directly in $(BUILD_UART) subdirectory
  plat: marvell: armada: a3k: Build intermediate files in $(BUILD_PLAT) directory
  plat: marvell: armada: a3k: Correctly set DDR_TOPOLOGY and CLOCKSPRESET for WTMI
  plat: marvell: armada: a3k: Allow use of the system Crypto++ library
  docs: marvell: Update info about WTP and MV_DDR_PATH parameters
  plat: marvell: armada: a3k: Add checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined
  docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
2021-02-02 10:43:10 +00:00
Pali Rohár ff46a41dc2 docs: marvell: Replace ESPRESSObin-Ultra TF-A build example by full example how to build production release of Marvell firmware image
ESPRESSObin-Ultra TF-A build example was now just a copy+paste of previous
mentioned example. It produced debug binary with custom log level, which
was not described. So rather replace this duplicate build example by a full
example with all steps how to build production release of Marvell firmware
image for EspressoBin with 1GHz CPU and 1GB DDR4 RAM.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ief1b8bc96a3035ebd8421bd68dca5eb5c8d8fd52
2021-02-02 10:26:34 +01:00
Pali Rohár f60f1e848d docs: marvell: Fix description of flash-image.bin image
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I192acab2a7f42cd80069faeac2d7823a05558dc6
2021-02-02 10:26:34 +01:00
Pali Rohár 23abf07ce4 docs: marvell: Add information into CLOCKSPRESET option how to identify CPU frequency
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1
2021-02-02 10:26:34 +01:00
Pali Rohár 9c3fffdc86 docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra board
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I96c2d9d5bc6c69a1a66a29bf586a23375d63ab5a
2021-02-02 10:26:34 +01:00
Pali Rohár 24e6e10b99 docs: marvell: Move Supported Marvell platforms to PLAT build option
Reformat list of boards, remove unsupported OcteonTX2 and mention
supported Turris MOX board.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I22cea7f77fd078554c7f0ed4108781626209e563
2021-02-02 10:25:49 +01:00
Pali Rohár 711a6bb79b docs: marvell: Update info about WTMI_IMG option
Default WTMI_IMG value was documented incorrectly. Also WTMI_IMG name may
be misleading as this option does not specify full WTMI image, just a main
loop (e.g. fuse.bin or custom RTOS image) without hardware initialization
code (DDR, CPU and clocks).

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I3de4a27ce2165b962fa628c992fd8f80151efd7c
2021-01-29 17:46:50 +01:00
Pali Rohár 33af2937cd docs: marvell: Update info about BOOTDEV=SATA
Information is taken from the post https://lists.denx.de/pipermail/u-boot/2017-July/299351.html

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5f608e135ec56685a3e2b986a52670540d48a4bf
2021-01-29 17:46:50 +01:00
Pali Rohár 8b92097366 plat: marvell: armada: a3k: Add a new target mrvl_uart which builds UART image
This change separates building of flash and UART images, so it is possible
to build only one of these images. Also this change allows make to build
them in parallel.

Target mrvl_flash now builds only flash image and mrvl_uart only UART
image. This change reflects it also in the documentation.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ie9ce4538d52188dd26d99dfeeb5ad171a5b818f3
2021-01-29 17:46:50 +01:00
Pali Rohár 8708a884ae plat: marvell: armada: a3k: Allow use of the system Crypto++ library
This change introduces two new A3720 parameters, CRYPTOPP_LIBDIR and
CRYPTOPP_INCDIR, which can be used to specify directory paths to
pre-compiled Crypto++ library and header files.

When both new parameters are specified then the source code of Crypto++ via
CRYPTOPP_PATH parameter is not needed. And therefore it allows TF-A build
process to use system Crypto++ library.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6d440f86153373b11b8d098bb68eb7325e86b20b
2021-01-29 17:46:50 +01:00
Pali Rohár 494be3ee0e docs: marvell: Update info about WTP and MV_DDR_PATH parameters
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id5e36b7ba3a840cb3598c580e806b52d8e8dd70f
2021-01-28 14:21:23 +01:00
Madhukar Pappireddy 26dccba6dd Merge changes from topic "scmi-msg" into integration
* changes:
  doc: maintainers: add scmi server
  drivers: move scmi-msg out of st
2021-01-27 15:14:46 +00:00
Manish Pandey 70311692f1 Merge "Fix documentation typos and misspellings" into integration 2021-01-26 15:24:52 +00:00
Pali Rohár 1cea02133f docs: marvell: Update mv-ddr-marvell and A3700-utils-marvell branches
Marvell finally started providing the latest version of mv-ddr-marvell and
A3700-utils-marvell code in master branch of their git repositories.
Reflect this in build instructions.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I08d1189dac60eb2a28335c68f611c1da634106f6
2021-01-26 10:44:07 +01:00
Peng Fan 12b66a9195 doc: maintainers: add scmi server
Add maintainer entry for scmi server

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I673d7395a8cea3b553832e330c8a8ce37f8c2a5c
2021-01-25 21:59:12 +08:00
Madhukar Pappireddy 49e4a5fcad Merge "docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions" into integration 2021-01-24 18:15:43 +00:00
David Horstmann 47147013b4 Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation.

Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
2021-01-21 12:51:31 +00:00
Manish Pandey 6b2924bbbf Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration
* changes:
  doc: renesas: Update RZ/G2 code owner list
  plat: renesas: rzg: DT memory node enhancements
  renesas: rzg: emmc: Enable RZ/G2M support
  plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support
  drivers: renesas: rzg: Add HiHope RZ/G2M board support
  tools: renesas: Add tool support for RZ/G2 platforms
2021-01-20 17:26:36 +00:00
Madhukar Pappireddy 6047a10538 Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes:
  doc: renesas: Update code owner for Renesas platforms
  doc: renesas: Document platforms based on RZ/G2 SoC's
  renesas: rzg: Add PFC support for RZ/G2M
  renesas: rzg: Add QoS support for RZ/G2M
  renesas: rzg: Add support for DRAM initialization
2021-01-15 15:39:13 +00:00
Lauren Wehrmeister 337e493306 Merge changes I36e4d672,I47610cee into integration
* changes:
  Workaround for Cortex N1 erratum 1946160
  Workaround for Cortex A78 erratum 1951500
2021-01-14 22:45:20 +00:00
Luka Kovacic d0b367b77a docs: marvell: armada: Update MARVELL_PLATFORM list and build instructions
The supported MARVELL_PLATFORM list is updated to include the recently added
a80x0_puzzle platform (IEI Puzzle-M801).

Additionally building instructions are added for the GST ESPRESSObin-Ultra
board (1 GB, DDR4 RAM variant), which has been tested successfully and booted
TF-A on the board.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Change-Id: Ie5724df27c1ee2e8f6a52664520579e872471e93
2021-01-14 14:34:42 +01:00
johpow01 263ee781c6 Workaround for Cortex N1 erratum 1946160
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1.  The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics.  This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2021-01-13 19:56:07 +00:00
johpow01 3a2710dcab Workaround for Cortex A78 erratum 1951500
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1.  The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics.  This workaround
works on revisions r1p0 and r1p1, in r0p0 there is no workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
2021-01-13 13:54:18 -06:00
Biju Das afda405b3d doc: renesas: Update RZ/G2 code owner list
Add Lad Prabhakar as the code owner for the newly added
RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ic9bacaf31d653e1e553fa70043053805f56a2b84
2021-01-13 19:15:57 +00:00
Biju Das d60642a467 doc: renesas: Update code owner for Renesas platforms
Add Marek Vasut as the code owner for the common code shared by
both Renesas R-Car and RZ/G2 platforms.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I3c0a402f4663ffcf4d2df408a3ccd4d1a8629b3a
2021-01-13 19:15:57 +00:00
Biju Das 2bc485858b doc: renesas: Document platforms based on RZ/G2 SoC's
Document the platforms based on RZ/G2 SoC's.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I9ce5b9df3573b1198c5c7be79b5471d54573609a
2021-01-13 19:15:57 +00:00
Aditya Angadi 06ea86fee8 docs: update fvp version to be used for rdv1 platform
Move RD-V1 platform to use version of FVP_RD_Daniel from 11.10 build 36
to 11.13 build 10

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I9622c03d342bb780234dec8ffe4ab11d8069acab
2021-01-13 22:51:05 +05:30
johpow01 e26c59d2c9 Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1.  The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.

SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
2021-01-12 18:06:37 +00:00
Manish Pandey fde125cb61 Merge "plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor" into integration 2021-01-06 18:24:22 +00:00