Commit Graph

1665 Commits

Author SHA1 Message Date
André Przywara 4230998741 Merge changes Icf5e3045,Ie5fb0b72 into integration
* changes:
  docs(allwinner): update SoC list and build options
  docs(allwinner): add SUNXI_SETUP_REGULATORS build option
2022-01-06 19:14:29 +01:00
Andre Przywara f2b2cc146e docs(allwinner): update SoC list and build options
Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936
2021-12-27 15:32:22 +00:00
Andre Przywara aa61699027 docs(allwinner): add SUNXI_SETUP_REGULATORS build option
Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a
2021-12-27 15:32:22 +00:00
Madhukar Pappireddy b48121b6fd Merge "fix(errata): workaround for Cortex X2 erratum 2058056" into integration 2021-12-22 15:23:00 +01:00
Bipin Ravi 47833abd77 Merge "fix(errata): workaround for Cortex X2 erratum 2002765" into integration 2021-12-22 01:12:32 +01:00
Bipin Ravi c2d75fa7a3 Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration 2021-12-22 01:10:54 +01:00
Mark Dykes c8076a0e69 Merge "fix(doc): update TF-A v2.7 release date in the release information page" into integration 2021-12-21 19:08:44 +01:00
johpow01 e16045de50 fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)

However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
2021-12-21 11:52:26 -06:00
Bipin Ravi 3e80e840c1 fix(doc): update TF-A v2.7 release date in the release information page
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iae84f82518ab89edc204a23083d5f4168449c2bf
2021-12-21 09:14:48 -06:00
johpow01 34ee76dbdf fix(errata): workaround for Cortex X2 erratum 2002765
Cortex X2 erratum 2002765 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I11576a03bfd8a6b1bd9ffef4430a097d763ca3cf
2021-12-17 18:23:59 +01:00
johpow01 1db6cd6027 fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
2021-12-16 23:22:27 +01:00
Madhukar Pappireddy e6b1a9abb6 Merge "feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support" into integration 2021-12-16 17:18:01 +01:00
Madhukar Pappireddy e119c2056c Merge "docs(ff-a): boot order field of SPs manifest" into integration 2021-12-16 15:17:08 +01:00
Gary Morrison dc669220d5 feat(plat/fvp_r): Threat Model for TF-A v8-R64 Support
Threat model for the current, BL1-only R-class support.

Signed-off-by: Gary Morrison <gary.morrison@arm.com>
Change-Id: I8479d5cb30f3cf3919281cc8dc1f21cada9511e0
2021-12-16 08:10:35 -06:00
J-Alves c1ff1791f7 docs(ff-a): boot order field of SPs manifest
Document `boot-order` field from FF-A partitions manifest, in accordance
to Hafnium's (SPM) implementation.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9fd070100ee52e0d465d2cce830cc91d78bddfc0
2021-12-16 09:24:56 +00:00
Manish Pandey a5645148a6 Merge changes from topic "jc/AMUv1" into integration
* changes:
  docs(build-options): add build macros for features FGT,AMUv1 and ECV
  fix(amu): fault handling on EL2 context switch
2021-12-13 13:52:37 +01:00
Jayanth Dodderi Chidanand 6401776747 docs(build-options): add build macros for features FGT,AMUv1 and ECV
This patch adds macros explicit to the features - FEAT_FGT,FEAT_AMUv1
and FEAT_ECV respectively. It assists in controlled access to the set
of registers (HDFGRTR_EL2, HAFGRTR_EL2 and CNTPOFF_EL2) under the
influence of these features during context save and restore routines.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I5082ea6687a686d8c5af3fe8bf769957cf3078b0
2021-12-10 12:36:02 +00:00
Manish V Badarkhe 43997d2257 docs(measured-boot): add a platform function for critical data
Added a platform function to measure the critical data and record its
measurement.
Also, corrected a return value of 'plat_mboot_measure_image' function
in the documentation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I576676f654e517c2010ca1d5a87a1f7277d581c3
2021-12-08 13:09:30 +00:00
Manish V Badarkhe 8b3e2cc7bc fix(docs): update the v2.6 change-log
Updated the v2.6 change-log for below:
1. Moved ETE/ETM related changes under separate scope
2. Added manually commit log for Demeter CPU

Change-Id: Ib5b5f994f603af6c82b1400256752581a7931268
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-12-07 18:12:55 +01:00
Yann Gautier 53863c845d docs: mark STM32MP_USE_STM32IMAGE as deprecated
This macro was used for the legacy boot mode on SPM32MP platforms.
The recommended boot method is now FIP.
The code under this macro will be removed after tag v2.7.

Change-Id: Id3b7baea2d3e6ea8b36a4cd0b107cb92591a172b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-06 17:40:23 +01:00
Rex-BC Chen 27132f13ca feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
2021-12-01 16:36:28 +01:00
Olivier Deprez d605439900 Merge "docs(spm): update threat model with FF-A v1.1" into integration 2021-11-26 09:58:13 +01:00
J-Alves 668ce500f9 docs(spm): update threat model with FF-A v1.1
Update SPM's threat model to contain threats related to notifications
feature, compliant with FF-A v1.1 spec.

Change-Id: I4a825be5dd14137a0d04d532adfe5343714794c5
Signed-off-by: J-Alves <joao.alves@arm.com>
2021-11-23 17:30:40 +00:00
Manish V Badarkhe 63d2e96042 docs(changelog): generate changelog
For future reference, this changelog was generated with the following
command:

    npm run release -- --skip.commit --skip.tag --release-as 2.6.0

Change-Id: Idf6be5c3be15ddfdb1d32fafb9e0e4b399b269f3
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-11-22 23:08:12 +00:00
Olivier Deprez f92b00187a Merge "docs(ff-a): update documentation of FF-A interfaces" into integration 2021-11-22 18:38:07 +01:00
J-Alves 16c1c45326 docs(ff-a): update documentation of FF-A interfaces
- Overview of FF-A v1.1 notifications feature, and list of all
the new related interface.
- FFA_RXTX_UNMAP now implemented, so provided description.
- FF-A v1.1 interfaces documented: FFA_SPM_ID_GET and
FFA_SECONDARY_EP_REGISTER.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If40b4d2b2473f81ecfb2ddbf14852c3f10682867
2021-11-18 14:41:28 +00:00
Chris Kay 7d3b519372 docs(commit-style): add commit style documentation
This change adds a new documentation page describing the commit style,
acceptable Conventional Commits types and scopes, and documents the
process for expanding the list of scopes.

Change-Id: Iad957b67fa71a879e8aa0790c58a5b08cec300d6
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:37 +00:00
Chris Kay c4e8edab21 build(docs): introduce release script
This change introduces a new NPM run script to automatically generate
the release changelog, as well as bump version numbers across the
code-base and create the release tag.

This script runs [Standard Version] to execute this, which is a tool
designed around automating substantial parts of the release process.
This can be done by running:

    npm run release -- [<standard-version args>]

Standard Version expects the project to adhere to the [Semantic
Versioning] convention which TF-A does not, so you may need to specify
the version manually, e.g.:

    npm run release -- --release-as 2.6.0

Individual steps of the release process may also be skipped at-will,
which may be necessary when, for example, tweaking the changelog:

    npm run release -- --skip.commit --skip.tag

Standard Version is configured by the `.versionrc.js` file, which
contains information about the Conventional Commits types and scopes
used by the project, and how they map to the changelog.

To maintain continuity with the existing changelog style - at least to
the extent possible in the move from manual to automatic creation - a
customized changelog template has been introduced, based on the
Conventional Commits template provided by Standard Version.

This template package extends the Conventional Commits template package
by introducing support for parsing the Conventional Commits scopes into
changelog sections, similarly to how they were previously organized.

[Standard Version]:
https://github.com/conventional-changelog/standard-version
[Semantic Versioning]: https://semver.org

Change-Id: I5bafa512daedc631baae951651c38c1c62046b0a
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:37 +00:00
Chris Kay c76556a017 build(docs): add support for Markdown documentation
This changes adds support for building Markdown documentation into
Sphinx with [MyST]. We'll make use of this in a later patch, where we
introduce automatically-generated Markdown documentation that needs to
be compiled as part of the Sphinx documentation.

[MyST]: https://myst-parser.readthedocs.io/en/latest

Change-Id: I2a241a588c579fac1a81e1853479908928be1fc8
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:36 +00:00
Chris Kay 35cc497d0a docs(prerequisites): update to Node.js v16
Updates the Node.js version installed by the prerequisite instructions
from v14 to v16, which is the latest LTS release.

The instructions for installing the Node Version Manager (NVM) have
also been updated for v0.39.0 (previously v0.38.0).

Change-Id: I85528b3906305914ba6169b4dc5aafcf5b36a339
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:35 +00:00
Chris Kay 2167c02d65 build(docs): update Python dependencies
Updates the Python dependencies used to build the project's Sphinx
documentation to their latest versions.

Change-Id: I8baee89c85179a667a3850a7b9705ab76f4d702a
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:35 +00:00
Chris Kay a539c77185 build(docs): pin Python dependencies
Recently some of our dependencies' dependencies have come into conflict
and are now causing errors when trying to install the Python
requirements. This change introduces `requirements.in` - a list of our
own direct dependencies, and pins them to specific versions.

The existing `requirements.txt` file is now automatically generated by
the `pip-compile` tool - part of the pip-tools package - and ensures
that our dependency tree is also pinned. This is a manual process at
present, but our dependencies are updated infrequently enough that it's
not introducing any major overhead.

Change-Id: I3cd0c11a1a4eccaf0d77b538cfdb94474833b811
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:34 +00:00
Chris Kay a61940ca73 fix(docs): fix `FF-A` substitution
In this change the `FFA` substitution has been renamed to `FF-A`, as
well as the term it substitutes to - the `FFA` term does not exist.

Change-Id: I0c33d00d82a5498f7088e6a2b088a0006dfe7f65
Signed-off-by: Chris Kay <chris.kay@arm.com>
2021-11-17 16:04:34 +00:00
Olivier Deprez 095342d3e4 Merge "docs(spm): document s-el0 partition support" into integration 2021-11-17 13:54:04 +01:00
Manish Pandey d5c70fa9f9 Merge "fix(spm_mm): do not compile if SVE/SME is enabled" into integration 2021-11-16 23:30:55 +01:00
Manish Pandey 4333f95bed fix(spm_mm): do not compile if SVE/SME is enabled
As spm_mm cannot handle SVE/SME usage in NS world so its better to give
compilation error when ENABLE_SVE_FOR_NS=1 or ENABLE_SME_FOR_NS=1.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I69dbb272ca681bb020501342008eda20d4c0b096
2021-11-16 16:06:33 +00:00
Zelalem Aweke 7446c266c9 docs(rme): add description of TF-A changes for RME
This patch expands the RME documentation with description of TF-A
changes for RME. It also modifies some other parts of TF-A documentation
to account for RME changes.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9e6feeee235f0ba4b767d239f15840f1e0c540bb
2021-11-15 22:20:07 +01:00
johpow01 6ee92598cf docs(gpt): add documentation page for GPT library
This patch adds some documentation for the GPT library as well as adds
code owners for it.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If1cd79626eadb27e1024d731b26ee2e20af74a66
2021-11-15 23:17:04 +02:00
johpow01 dc78e62d80 feat(sme): enable SME functionality
This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable
SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions
in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these
traps, but support for SME context management does not yet exist in
SPM so building with SPD=spmd will fail.

The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot
be used with SME as it is a superset of SVE and will enable SVE and
FPU/SIMD along with SME.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
2021-11-12 10:38:00 -06:00
Madhukar Pappireddy 52558e080d docs(spm): secure interrupt management in SPMC
Change-Id: I9bed67e4146ae92123ab925334e37fb0d3677ef1
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-11-10 16:07:33 -06:00
Joanna Farley f7a8354481 Merge "feat(measured boot): add documentation to build and run PoC" into integration 2021-11-09 16:08:25 +01:00
Madhukar Pappireddy 0b5e33c7aa Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration
* changes:
  fix(errata): workaround for Neoverse V1 erratum 2216392
  fix(errata): workaround for Cortex A78 erratum 2242635
  fix(errata): workaround for Neoverse-N2 erratum 2280757
  fix(errata): workaround for Neoverse-N2 erratum 2242400
  fix(errata): workaround for Neoverse-N2 erratum 2138958
  fix(errata): workaround for Neoverse-N2 erratum 2242415
2021-11-08 15:28:19 +01:00
Javier Almansa Sobrino a125c55623 feat(measured boot): add documentation to build and run PoC
Add documentation to build and run a PoC based on the OP-TEE toolkit
to show how TF-A Measured Boot can interact with a third party (f)TPM
service.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I11ac99c4ff54ea52aba0731aa7f707d7cd0c4216
2021-11-08 10:49:26 +00:00
johpow01 4c8fe6b17f fix(errata): workaround for Neoverse V1 erratum 2216392
Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core.
It applies to revisions r1p0 and r1p1 and is still open. The issue is
also present in r0p0 but there is no workaround in that revision.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab
2021-11-05 23:10:58 +01:00
Raghu Krishnamurthy aeea04d44d docs(spm): document s-el0 partition support
This patch adds a brief description of S-EL0 partition support in the
SPMC using ARMv8.1 FEAT_VHE.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Ie079265476604f62d5f2a66684f01341000969d0
2021-11-05 14:32:44 -07:00
johpow01 1ea9190c6a fix(errata): workaround for Cortex A78 erratum 2242635
Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core.
It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue
is also present in r0p0 but there is no workaround for this revision.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07
2021-11-05 20:52:41 +02:00
nayanpatel-arm 0d2d99924e fix(errata): workaround for Neoverse-N2 erratum 2280757
Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add
2021-11-04 13:01:13 -07:00
nayanpatel-arm 603806d137 fix(errata): workaround for Neoverse-N2 erratum 2242400
Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[17] to 1'b1 followed by setting few
system control registers to specific values as per attached
SDEN document.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649
2021-11-04 12:51:26 -07:00
nayanpatel-arm c948185c97 fix(errata): workaround for Neoverse-N2 erratum 2138958
Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[13] to 1'b1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720
2021-11-04 20:30:19 +01:00
nayanpatel-arm 5819e23bc4 fix(errata): workaround for Neoverse-N2 erratum 2242415
Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I442be81fbc32e21fed51a84f59584df17f845e96
2021-11-04 12:13:22 -07:00