This patch fixes an issue when secure world timing information
can be leaked because Secure Cycle Counter is not disabled.
For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD
bit on CPU cold/warm boot.
For the earlier architectures PMCR_EL0 register is saved/restored
on secure world entry/exit from/to Non-secure state, and cycle
counting gets disabled by setting PMCR_EL0.DP bit.
'include\aarch64\arch.h' header file was tided up and new
ARMv8.5-PMU related definitions were added.
Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Pull out common code from aarch64 and include
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
The CPU[1-3] are reset to initial/cold boot state (with their reset
address set to 0x0). In this state the cpus are waiting for another
one to set the reset address to bl31_warm_entrypoint and wake them up.
The CPU0 needs a bit of a workaround as changing the reset address
either through PSCI mailbox or the mmio mapped RVBAR (at 0xda834650)
does not seem to have any effect. Thus the workaround consists in
emulating the other CPUs' behavior with a WFE loop and manually jumping
to bl31_warm_entrypoint when woken back up by another one.
Change-Id: I11265620b5fd0619285e3993253a3f9a3ff6a7a4
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Before CPU enters standby state (wfi), the AP needs to signal the SCP
through PSCI mailbox.
Also at boot time the AP has to wait for the SCP to be ready before
sending the first scpi commands or it can crash.
Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.
All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.
Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
At the time of writting, GCC 8.3-2019.03 is the latest version available
on developer.arm.com.
Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to
have a finer control on the use of floating-point and SIMD instructions.
Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Pull out common code from agilex and stratix10
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
Fix the typo "warn" -> "warm".
Also fix the following checkpatch.pl warnings:
CHECK: Prefer using the BIT macro
CHECK: No space is necessary after a cast
CHECK: Alignment should match open parenthesis
CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle
Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the helper in utils_def.h instead of the own macro.
Change-Id: I527f9e75914d60f66354e365006b960ba5e8cbae
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This change is needed for the platform to compile following the changes
made in commits cbdc72b559 and 3e02c7436c.
Change-Id: I3468dd27f3b4f3095fb82f445d51cd8714311eb7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
This patch adds gicv3 support for qemu, in order not to break any legacy
use case, gicv2 is still set by default, gicv3 can be selected by
compiling parameter QEMU_USE_GIC_DRIVER=QEMU_GICV3.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: Ic63f38abf16ed3c36aa60e80d50103cf05cf797b
This file moves gicv2 codes to a new separate files, target is to add
gicv3 support later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"
This is treated as an error since commit 93c690eba8 ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")
Only the actual errors are being tackled by this patch. It is up to the
platform to choose whether there needs to be further modifications to
the code.
Change-Id: I70860ae5f2a34d7c684bd491b76da50aa04f778e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile
Change-Id: I89565127c67eff510e48e21fd450af4c3088c2d4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Add support for multiple Cryptocell revisions which
use different APIs.
This commit only refactors the existing code in preperation to the addition
of another Cryptocell revisions later on.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I16d80b31afb6edd56dc645fee5ea619cc74f09b6
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
API and products.
Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_helper()
Add helper to parse BL31 parameters (both versions)
Factor out cross-BL API into export headers suitable for 3rd party code
Use explicit-width data types in AAPCS parameter structs
plat/rockchip: Switch to use new common BL aux parameter library
Introduce lightweight BL platform parameter library
The Mediatek MT8173/MT8183 SoCs are prime candidates for switching to
the new bl31_params_parse() helper, so switch them over. This will allow
BL2 implementations on these platforms to transparently switch over to
the version 2 parameter structure.
Change-Id: I0d17ba6c455102d325a06503d2078a76d12b5deb
Signed-off-by: Julius Werner <jwerner@chromium.org>
The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementations on this platform to transparently switch over to the
version 2 parameter structure.
Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
This patch introduces an additional precautionary step to further
enhance protection against variant 4. During the context initialisation
before we enter the various BL stages, the SPSR.SSBS bit is explicitly
set to zero. As such, speculative loads/stores are by default disabled
for all BL stages when they start executing. Subsequently, each BL
stage, can choose to enable speculative loads/stores or keep them
disabled.
This change doesn't affect the initial execution context of BL33 which
is totally platform dependent and, thus, it is intentionally left up to
each platform to initialise.
For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means
that, for Arm platforms, all BL stages start with speculative
loads/stores disabled.
Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"
This is treated as an error since commit 93c690eba8 ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")
Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
BL31 used to take a single bl31_params_t parameter structure with entry
point information in arg0. In commit 726002263 (Add new version of image
loading.) this API was changed to a more flexible linked list approach,
and the old parameter structure was copied into all platforms that still
used the old format. This duplicated code unnecessarily among all these
platforms.
This patch adds a helper function that platforms can optionally link to
outsource the task of interpreting arg0. Many platforms are just
interested in the BL32 and BL33 entry point information anyway. Since
some platforms still need to support the old version 1 parameters, the
helper will support both formats when ERROR_DEPRECATED == 0. This allows
those platforms to drop a bunch of boilerplate code and asynchronously
update their BL2 implementation to the newer format.
Change-Id: I9e6475adb1a7d4bccea666118bd1c54962e9fc38
Signed-off-by: Julius Werner <jwerner@chromium.org>
Alexei Fedorov
Sandrine Bailleux
Hadi Asyrafi
Remi Pommarel
Julius Werner
Louis Mayencourt
Balint Dobszay
Masahiro Yamada
Ambroise Vincent
Soby Mathew
Hongbo Zhang
Madhukar Pappireddy
Gilad Ben-Yossef
John Tsichritzis