This new function pmic_voltages_init() is used to set the minimum value
for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved
from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibbe237cb5dccc1fddf92e07ffd3955048ff82075
This field is now declared on the 10 LSB bits on STM32MP13.
Several possible values are specified in the Reference Manual, and
indicate an open or closed device. Other values lead to a system panic.
Change-Id: I697124a21db66a56e7e223d601aa7cf44bb183c4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Update USB and DFU descriptor used for STM32MP13x
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I6e8111d279f49400a72baa12ff39f140d97e1c70
Add new clock driver for STM32MP13. Split the include file to manage
either STM32MP13 or STM32MP15.
Change-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Add dedicated clock and reset dt-bindings include files. The former
files are renamed with stm32mp15, and the stm32mp1 file just
determine through STM32MP13 or STM32MP15 flag which file to include.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0db23996a3ba25f7c3ea920f16230b11cf051208
The IDC register from DBGMCU is duplicated in SYSCFG. As SYSCFG is
always accessible, get chip ID and revision ID from there on STM32MP13.
Change-Id: Ib0b6e8f68a2934a45ec0012f69db6c12a60adb17
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The ERXCTLR_EL1 register reads are RES0 for some error records
leading to a false assert on a read back.
This patch removes the assert on reading back the ERXCTLR_EL1
register to fix this issue.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0cab30b12656a800ba87b8bb94b4c67a2331dee6
Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and
Cortex-A78C.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548
On STM32MP13, there is only 1 DDR port, hence only 1 TZC400 filter.
Change-Id: I4f6750022cdaf658cd209a4bf48a6cdb0717020e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Increase the fixed regulator number that needs to be
2 for STM32MP13.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ica990fe9a6494b76aed763d2d353f5234fed7cea
The header must now include by default at least an extra padding
header, increasing the size of the header to 512 bytes (0x200).
This header will be placed at the end of SRAM3 by BootROM, letting
the whole SYSRAM to TF-A.
The boot context is now placed in SRAM2, hence this memory has to be
mapped in BL2 MMU. This mapping is done for all SRAMs in a 2MB area.
Change-Id: I50fcd43ecd0ba2076292b057566efe6809b9971a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Add the new field for the new header v2.0.
Force MP13 platform to use v2.0.
Removing unused fields in boot_api_context_t for STM32MP13.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iac81aad9a939c1f305184e335e0a907ac69071df
Add the IP addresses that are STM32MP13 and update the ones for
which the base address has changed.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iea71a491da36f721bfd3fbfb010177e2a6a57281
Add the new part numbers and adapt the functions that use them.
There is no package number in OTP as they all share the same GPIO
banks.
This part is then stubbed for STM32MP13.
Change-Id: I13414326b140119aece662bf8d82b387dece0dcc
Signed-off-by: Yann Gautier <yann.gautier@st.com>
On STM32MP13, the chip revision Z is 0x1001, contrary to STM32MP15,
for which it was 0x2001.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If65482e824b169282abb5e26ca91e16ef7640b52
The backup register used on STM32MP15 to save the boot interface for
the next boot stage was 20. It is now saved in backup register 30
on STM32MP13.
Change-Id: Ibd051ff2eca7202184fa428ed57ecd4ae7388bd8
Signed-off-by: Yann Gautier <yann.gautier@st.com>
STM32MP13 is a single Cortex-A7 CPU, always return true in
stm32mp_is_single_core() function.
Change-Id: Icf36eaa887bdf314137eda07c5751cea8c950143
Signed-off-by: Yann Gautier <yann.gautier@st.com>
* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ.
* STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1
and reset from MCU traces
* There is no MCU on STM32MP13. Put MCU security management
under STM32MP15 flag.
* The authentication feature is not supported yet on STM32MP13,
put the code under SPM32MP15 flag.
* On STM32MP13, the monotonic counter is managed in ROM code, keep
the monotonic counter update just for STM32MP15.
* SYSCFG: put registers not present on STM32MP13 under STM32MP15
flag, as the code that manages them.
* PMIC: use ldo3 during DDR configuration only for STM32MP15
* Reset UART pins on USB boot is no more required.
Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
SYSRAM is only 128KB and starts at 0x2FFE0000.
SRAMs are added.
BL2 code and DTB sizes are also reduced to fit in 128KB.
Change-Id: I25da99ef5c08f8008ff00d38248d61b6045adad4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can be used as monitor.
STM32MP13 uses the header v2.0 format for stm32image generation
for BL2.
Change-Id: Ie5b0e3230c5e064fe96f3561fc5b3208914dea53
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The stm32image tool is updated to manage new header v2.0 for BL2
images.
Add new structure for the header v2.0 management.
Adapt to keep compatibility with v1.0.
Add the header version major and minor in the command line
when executing the tool, as well as binary type (0x10 for BL2).
Change-Id: I70c187e8e7e95b57ab7cfad63df314307a78f1d6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Add FF-A v1.1 FFA_RX_ACQUIRE ABI forwarding to SPMD.
RX acquire interface is used by Hypervisor to acquire ownership of a
VM's RX buffer from SPMC when it needs to deliver a message to the VM.
Change-Id: I5f57240a9c9e94eb696a5a394ec0644170380026
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery
hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to
enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3
is implemented for A57/A72 because some revisions are affected by both
CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace
SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details
of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c
Update WA for Errata A-050426 as Commands for
PEX (PEX1..PEX6) , lnx1_e1000#0, lnx1_xfi and
lnx2_xfi has been moved to PBI phase.
This patch requires RCW to include PBI commands
to write commands in BIST mode for PEX, lnx1_e1000,
lnx1_xfi and lnx2_xfi IP blocks.
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Change-Id: I27c2b055c82c0b58df83449f9082bfbfdeb65115
The code declares different types of parameters.
static bool message_id_is_supported(unsigned int message_id);
static bool message_id_is_supported(size_t message_id)
{
...
}
Signed-off-by: Schspa Shi <schspa@gmail.com>
Change-Id: I7435d3b9309ea5fb5f8e3daa7173e09322184422
Implements mitigation for Cortex-A72 CPU versions that support
the CSV2 feature(from r1p0). It also applies the mitigation for
Cortex-A57 CPU.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I7cfcf06537710f144f6e849992612033ddd79d33
In anticipation of Spectre BHB workaround mitigation patches, we
disable the RECLAIM_INIT_CODE for FVP platform. Since the spectre
BHB mitigation workarounds inevitably increase the size of the various
segments due to additional instructions and/or macros, these segments
cannot be fit in the existing memory layout designated for BL31 image.
The issue is specifically seen in complex build configs for FVP
platform. One such config has TBB with Dual CoT and test secure
payload dispatcher(TSPD) enabled. Even a small increase in individual
segment size in order of few bytes might lead to build fails due to
alignment requirements(PAGE_ALIGN to 4KB).
This is needed to workaround the following build failures observed
across multiple build configs:
aarch64-none-elf-ld.bfd: BL31 init has exceeded progbits limit.
aarch64-none-elf-ld.bfd: /work/workspace/workspace/tf-worker_ws_2/trusted_firmware/build/fvp/debug/bl31/bl31.elf section coherent_ram will not fit in region RAM
aarch64-none-elf-ld.bfd: BL31 image has exceeded its limit.
aarch64-none-elf-ld.bfd: region RAM overflowed by 4096 bytes
Change-Id: Idfab539e9a40f4346ee11eea1e618c97e93e19a1
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
DEBUG mode can be enabled without any issue for Armada 37xx and also for
other A7K/A8K/CN913x. There is no incompatibility with Xmodem protocol
like it was written before, because Armada 37xx UART images do not print
anything on UART during image transfer and A7K/A8K/CN913x BLE image
automatically turn off debugging output when booting over UART. Looks
like this incorrect information is some relict from the past.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I85adc3c21036656b4620c4692e04330cad11ea2f
This allows TF-A's a3700_system_reset() function to try Warm reset
method when CM3 reset method is not implemented by WTMI firmware.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I7303197373e1a8ca5a44ba0b1e90b48855d6c0c3
nutrs is set in ufs_enum (used by get_empty_slot), this will not
be assigned if UFS_FLAGS_SKIPINIT is set in flags during init and
might end up crashing read/write commands
Change-Id: I1517b69c56741fd5bf4ef0ebc1fc8738746233d7
Signed-off-by: anans <anans@google.com>
Fix software cache maintenance issues that can happen when
cpu prefetches data before DMA operations are complete.
This change fixes two cases one for ufs_read_blocks and
other for ufs_check_resp, in both cases invalidation of
buffer was done before the DMA operation completed.
This caused cpu prefetcher to bring data into cache
before DMA completed and caused UFS read failures.
The changes also removes unwanted cache operations to
local variable utrd which is not consumed by UFS host
controller and zeroing out buffer in ufs_read_capacity.
Change-Id: I9a288eb19d6705f6fa8bdb0b817a6411235fd8b6
Signed-off-by: Channagoud kadabi <kadabi@google.com>
* changes:
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert "feat(sgi): route TF-A logs via secure uart"
Revert "feat(sgi): add page table translation entry for secure uart"
new function for sending commands and reuses that function in the
driver, this can also be used to have retries for specific
commands in the future
Signed-off-by: anans <anans@google.com>
Change-Id: Ie01f36ff8e2df072db4d97929d293b80ed24f04b
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Change-Id: I28a370dd8b3a37087da621460eccc1acd7a30287
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Change-Id: I7c488aed9fcb70c55686d705431b3fe017b8927d
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Change-Id: I9bec02496f826e184c6efa643f869b2eb3b52539
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.
BUG=b:222217317
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I659ea1e0789cf135a71a13b752edaa35123e0941
When trying to boot from an SD card with STM32MP_EMMC_BOOT enabled,
booting fails with:
ERROR: Got unexpected value for active boot partition, 0
ASSERT: plat/st/common/bl2_stm32_io_storage.c:285
because SD cards don't provide a boot partition. So only try reading
from such a partition when booting from eMMC.
Fixes: 214c8a8d08 ("feat(plat/st): add STM32MP_EMMC_BOOT option")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Change-Id: I354b737a3ae3ea577e83dfeb7096df22275d852d
Re-factored the prior implementation of workaround for CVE-2018-3639
using branch and link instruction to save vector space to include the
workaround for CVE-2022-23960.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib3fe949583160429b5de8f0a4a8e623eb91d87d4
Yann Gautier
Nicolas Le Bayon
Patrick Delaunay
Gabriel Fernandez
Varun Wadekar
Madhukar Pappireddy
Bipin Ravi
Lionel Debieve
Lionel Debieve
Sebastien Pasdeloup
Federico Recanati
Wasim Khan
Schspa Shi
Manish Pandey
Pali Rohár
anans
Channagoud kadabi
Rex-BC Chen
Uwe Kleine-König
Joanna Farley