The F1 CAS latency setting was not bit shifted, which resulted in setting the DRAM additive latency value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org> |
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arm | ||
common | ||
compat | ||
mediatek | ||
nvidia/tegra | ||
qemu | ||
rockchip | ||
xilinx/zynqmp |