John Tsichritzis 63cc265886 Add cache flush after BL1 writes heap info to DTB ... A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we ensure that the heap info written to the DTB always gets written back to memory. Hence, sharing this info with other images is guaranteed. Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>		2018-09-07 11:45:55 +01:00
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allwinner	PSCI: Fix types of definitions	2018-07-20 13:49:22 +01:00
arm	Add cache flush after BL1 writes heap info to DTB	2018-09-07 11:45:55 +01:00
common	Prepare Mbed TLS drivers for shared heap	2018-09-04 10:32:06 +01:00
compat	Do not enable SVE on pre-v8.2 platforms	2017-11-30 17:45:23 +00:00
hisilicon	libc: Use printf and snprintf across codebase	2018-08-22 10:26:05 +01:00
imx	warp7: Add warp7 platform to the build	2018-09-04 14:18:31 +01:00
layerscape	Fix MISRA defects in BL31 common code	2018-08-30 09:22:33 +01:00
marvell	plat: marvell: Update Marvell base code version to 18.09.1	2018-09-03 16:06:18 +03:00
mediatek	PSCI: Fix types of definitions	2018-07-20 13:49:22 +01:00
nvidia/tegra	libc: Fix all includes in codebase	2018-08-22 10:26:05 +01:00
qemu	plat: qemu: update the early platform setup API	2018-09-04 15:20:26 +02:00
rockchip	libc: Fix all includes in codebase	2018-08-22 10:26:05 +01:00
rpi3	libc: Fix all includes in codebase	2018-08-22 10:26:05 +01:00
socionext	Fix MISRA defects in BL31 common code	2018-08-30 09:22:33 +01:00
st/stm32mp1	layerscape: stm32mp1: Migrate to enable_mmu_svc_mon()	2018-08-10 13:47:37 +01:00
ti/k3	ti: k3: common: Add basic PSCI core off support	2018-08-31 09:23:21 -05:00
xilinx/zynqmp	zynqmp: Define and enable ARM_XLAT_TABLES_LIB_V1	2018-09-04 18:33:02 +05:30