Chee Hong Ang 7f56f240d3 intel: clear 'PLAT_SEC_ENTRY' in early platform setup ... Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a		2020-10-24 11:00:42 +08:00
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aarch64	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
drivers	plat: intel: Fix CCU initialization for Agilex	2020-06-08 22:03:48 +00:00
include	intel: clear 'PLAT_SEC_ENTRY' in early platform setup	2020-10-24 11:00:42 +08:00
soc	Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration	2020-02-28 10:51:49 +00:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	plat: intel: Additional instruction required to enable global timer	2020-06-08 22:03:54 +00:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	intel: Fix argument type for mailbox driver	2020-02-25 16:41:47 +08:00
socfpga_sip_svc.c	Merge "intel: Fix argument type for mailbox driver" into integration	2020-02-28 10:23:10 +00:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00