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Bipin Ravi 7e3273e8e4 fix(errata): workaround for DSU-110 erratum 2313941 
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions
r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open.

The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable
clock gating of the SCLK domain. This will increase the idle power
consumption.

This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1781796/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
 		2022-05-11 19:05:36 +02:00
..
aem_generic.h cpus: Add casts to all definitions in CPU headers 2019-02-11 13:34:57 +00:00
cortex_a35.h Cortex-A35: Implement workaround for errata 855472 2019-04-17 13:46:43 +01:00
cortex_a53.h feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1 2022-01-13 18:00:46 +08:00
cortex_a55.h Cortex-A55: workarounds for errata 1221012 2019-05-28 14:19:04 +01:00
cortex_a57.h cpus: higher performance non-cacheable load forwarding 2020-02-20 09:25:45 -08:00
cortex_a65.h Introducing support for Cortex-A65 2019-10-02 18:12:28 +02:00
cortex_a65ae.h Introducing support for Cortex-A65AE 2019-10-03 15:38:31 +02:00
cortex_a72.h fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72 2022-03-16 16:35:07 -05:00
cortex_a73.h Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__ 2019-10-11 14:12:24 +02:00
cortex_a75.h Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ 2019-08-01 13:14:12 -07:00
cortex_a76.h fix(security): loop workaround for CVE-2022-23960 for Cortex-A76 2022-03-11 00:48:03 -06:00
cortex_a76ae.h fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C 2022-03-21 08:57:09 -05:00
cortex_a77.h fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00
cortex_a78.h fix(errata): workaround for Cortex A78 AE erratum 2395408 2022-03-24 10:55:48 +00:00
cortex_a78_ae.h fix(errata): workaround for Cortex A78 AE erratum 2395408 2022-03-24 10:55:48 +00:00
cortex_a78c.h fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C 2022-03-21 08:57:09 -05:00
cortex_a510.h fix(errata): workaround for Cortex-A510 erratum 2172148 2022-02-24 22:31:52 +01:00
cortex_a710.h fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00
cortex_hayes.h feat(cpu): add support for Hayes CPU 2021-09-30 19:30:39 +02:00
cortex_hunter.h feat(cpu): add support for Hunter CPU 2021-10-20 20:05:59 +02:00
cortex_makalu.h Add Makalu CPU lib 2021-03-01 17:11:36 -06:00
cortex_makalu_elp_arm.h Add "_arm" suffix to Makalu ELP CPU lib 2021-04-20 17:14:31 -05:00
cortex_x1.h fix(security): workaround for CVE-2022-23960 for Cortex-X1 2022-05-11 15:24:37 +02:00
cortex_x2.h fix(errata): workaround for Cortex-X2 erratum 2147715 2022-04-11 17:00:19 -05:00
cpu_macros.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
cpuamu.h Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ 2019-08-01 13:14:12 -07:00
denver.h lib: cpus: denver: add MIDR PN9 variant 2020-08-31 10:43:44 -07:00
dsu_def.h fix(errata): workaround for DSU-110 erratum 2313941 2022-05-11 19:05:36 +02:00
generic.h arm_fpga: Add support for unknown MPIDs 2020-09-25 15:45:50 +01:00
neoverse_demeter.h fix(cpu): correct Demeter CPU name 2021-10-21 20:12:28 +02:00
neoverse_e1.h Fix wrong MIDR_EL1 value for Neoverse E1 2019-03-15 15:40:27 +00:00
neoverse_n1.h fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00
neoverse_n2.h fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00
neoverse_n_common.h Add support for Neoverse-N2 CPUs. 2020-11-30 19:12:56 +00:00
neoverse_poseidon.h feat(cpu): add library support for Poseidon CPU 2022-01-28 11:12:21 +00:00
neoverse_v1.h fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00
qemu_max.h Add support for QEMU "max" CPU 2021-04-13 12:31:40 +01:00
rainier.h lib/cpus: update MIDR value for rainier cpu 2020-10-09 10:43:13 +00:00