arm-trusted-firmware/include
John Tsichritzis c250cc3b1b SSBS: init SPSR register with default SSBS value
This patch introduces an additional precautionary step to further
enhance protection against variant 4. During the context initialisation
before we enter the various BL stages, the SPSR.SSBS bit is explicitly
set to zero. As such, speculative loads/stores are by default disabled
for all BL stages when they start executing. Subsequently, each BL
stage, can choose to enable speculative loads/stores or keep them
disabled.

This change doesn't affect the initial execution context of BL33 which
is totally platform dependent and, thus, it is intentionally left up to
each platform to initialise.

For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means
that, for Arm platforms, all BL stages start with speculative
loads/stores disabled.

Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-24 12:49:53 +01:00
..
arch SSBS: init SPSR register with default SSBS value 2019-07-24 12:49:53 +01:00
bl1 BL1: Enable pointer authentication support 2019-02-27 11:58:09 +00:00
bl2 BL2_AT_EL3: Enable pointer authentication support 2019-02-27 11:58:09 +00:00
bl2u Standardise header guards across codebase 2018-11-08 10:20:19 +00:00
bl31 BL31: Enable pointer authentication support 2019-02-27 11:58:10 +00:00
bl32 sp_min: make sp_min_warm_entrypoint public 2019-04-25 13:37:56 +02:00
common Add support for Branch Target Identification 2019-05-24 14:44:45 +01:00
drivers Update base code to not rely on undefined overflow behaviour 2019-07-12 09:12:19 +01:00
dt-bindings stm32mp1: update device tree files 2019-01-18 15:45:08 +01:00
lib Merge "AArch64: Add 128-bit integer types definitions" into integration 2019-07-12 08:37:24 +00:00
plat n1sdp: add code for DDR ECC enablement and BL33 copy to DDR 2019-06-26 14:07:51 +01:00
services Remove support for the SMC Calling Convention 2.0 2019-01-30 16:01:49 +00:00
tools_share Sanitise includes across codebase 2019-01-04 10:43:17 +00:00