Varun Wadekar db891f32f6 Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms ... Many simulation/emulation platforms do not support this hardware block leading to SErrors during register accesses. This patch conditionally accesses the registers from this block only on actual Si and FPGA platforms. Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2020-01-23 09:02:29 -08:00
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drivers	Tegra194: toggle SE clock during context save/restore	2020-01-23 08:58:38 -08:00
plat_memctrl.c	Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1	2020-01-23 09:01:56 -08:00
plat_psci_handlers.c	Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms	2020-01-23 09:02:29 -08:00
plat_secondary.c	Tegra194: helper functions for CPU rst handler and SMMU ctx offset	2019-11-28 11:14:21 -08:00
plat_setup.c	Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms	2020-01-23 09:02:29 -08:00
plat_sip_calls.c	Tegra194: cleanup references to Tegra186	2019-11-28 11:14:21 -08:00
plat_smmu.c	Tegra194: smmu: add support for backup multiple smmu regs	2019-12-10 09:59:40 -08:00
plat_trampoline.S	Tegra194: smmu: add support for backup multiple smmu regs	2019-12-10 09:59:40 -08:00
platform_t194.mk	Tegra194: toggle SE clock during context save/restore	2020-01-23 08:58:38 -08:00