Abdul Halim, Muhammad Hadi Asyrafi ef51b097bf fix(intel): fix fpga config write return mechanism ... This revert commit 279c8015fefcb544eb311b9052f417fc02ab84aa. The previous change breaks this feature compatibility with Linux driver. Hence, the fix for the earlier issue is going to be fixed in uboot instead. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I93220243bad65ed53322050d990544c7df4ce66b		2022-04-28 22:25:05 +08:00
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aarch64	feat(intel): add macro to switch between different UART PORT	2022-04-05 14:25:30 +08:00
drivers	feat(intel): enable firewall for OCRAM in BL31	2022-04-28 19:08:35 +08:00
include	feat(intel): add SiP service for DCMF status	2022-04-28 22:21:01 +08:00
sip	feat(intel): add SMC support for ROM Patch SHA384 mailbox	2022-04-05 14:23:26 +08:00
soc	feat(intel): enable firewall for OCRAM in BL31	2022-04-28 19:08:35 +08:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	plat: intel: Additional instruction required to enable global timer	2020-06-08 22:03:54 +00:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	fix(intel): fix ECC Double Bit Error handling	2022-03-09 09:14:16 +08:00
socfpga_sip_svc.c	fix(intel): fix fpga config write return mechanism	2022-04-28 22:25:05 +08:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00