2013-10-25 09:08:21 +01:00
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/*
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2015-03-30 17:15:16 +01:00
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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2013-10-25 09:08:21 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_H__
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#define __ARCH_H__
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/*******************************************************************************
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* MIDR bit definitions
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******************************************************************************/
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2014-08-14 11:33:56 +01:00
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#define MIDR_IMPL_MASK 0xff
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#define MIDR_IMPL_SHIFT 0x18
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2014-08-14 16:19:29 +01:00
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#define MIDR_VAR_SHIFT 20
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2014-09-22 12:11:36 +01:00
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#define MIDR_VAR_BITS 4
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2014-08-14 16:19:29 +01:00
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#define MIDR_REV_SHIFT 0
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2014-09-22 12:11:36 +01:00
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#define MIDR_REV_BITS 4
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2013-10-25 09:08:21 +01:00
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#define MIDR_PN_MASK 0xfff
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#define MIDR_PN_SHIFT 0x4
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/*******************************************************************************
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* MPIDR macros
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******************************************************************************/
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#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
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#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
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#define MPIDR_AFFINITY_BITS 8
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#define MPIDR_AFFLVL_MASK 0xff
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#define MPIDR_AFF0_SHIFT 0
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#define MPIDR_AFF1_SHIFT 8
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#define MPIDR_AFF2_SHIFT 16
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#define MPIDR_AFF3_SHIFT 32
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#define MPIDR_AFFINITY_MASK 0xff00ffffff
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#define MPIDR_AFFLVL_SHIFT 3
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#define MPIDR_AFFLVL0 0
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#define MPIDR_AFFLVL1 1
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#define MPIDR_AFFLVL2 2
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#define MPIDR_AFFLVL3 3
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2015-02-26 15:25:58 +00:00
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#define MPIDR_AFFLVL0_VAL(mpidr) \
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((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL1_VAL(mpidr) \
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((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL2_VAL(mpidr) \
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((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL3_VAL(mpidr) \
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((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
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2014-12-04 14:14:12 +00:00
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/*
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* The MPIDR_MAX_AFFLVL count starts from 0. Take care to
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* add one while using this macro to define array sizes.
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* TODO: Support only the first 3 affinity levels for now.
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*/
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2013-10-25 09:08:21 +01:00
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#define MPIDR_MAX_AFFLVL 2
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/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
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#define FIRST_MPIDR 0
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2014-06-02 15:44:43 +01:00
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/*******************************************************************************
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* Definitions for CPU system register interface to GICv3
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******************************************************************************/
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#define ICC_SRE_EL1 S3_0_C12_C12_5
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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2015-09-03 14:18:02 +01:00
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#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
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#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
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#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
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#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
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#define ICC_IAR0_EL1 S3_0_c12_c8_0
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#define ICC_IAR1_EL1 S3_0_c12_c12_0
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#define ICC_EOIR0_EL1 S3_0_c12_c8_1
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#define ICC_EOIR1_EL1 S3_0_c12_c12_1
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2014-06-02 15:44:43 +01:00
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2013-10-31 11:27:43 +00:00
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets
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******************************************************************************/
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#define CNTCR_OFF 0x000
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#define CNTFID_OFF 0x020
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#define CNTCR_EN (1 << 0)
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#define CNTCR_HDBG (1 << 1)
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2014-03-31 11:25:18 +01:00
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#define CNTCR_FCREQ(x) ((x) << 8)
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2013-10-31 11:27:43 +00:00
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2013-10-25 09:08:21 +01:00
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/*******************************************************************************
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* System register bit definitions
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******************************************************************************/
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/* CLIDR definitions */
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#define LOUIS_SHIFT 21
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#define LOC_SHIFT 24
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#define CLIDR_FIELD_WIDTH 3
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/* CSSELR definitions */
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#define LEVEL_SHIFT 1
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/* D$ set/way op type defines */
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#define DCISW 0x0
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#define DCCISW 0x1
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#define DCCSW 0x2
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/* ID_AA64PFR0_EL1 definitions */
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#define ID_AA64PFR0_EL0_SHIFT 0
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#define ID_AA64PFR0_EL1_SHIFT 4
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#define ID_AA64PFR0_EL2_SHIFT 8
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#define ID_AA64PFR0_EL3_SHIFT 12
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#define ID_AA64PFR0_ELX_MASK 0xf
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2015-09-03 14:18:02 +01:00
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#define ID_AA64PFR0_GIC_SHIFT 24
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#define ID_AA64PFR0_GIC_WIDTH 4
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#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1)
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2013-10-25 09:08:21 +01:00
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/* ID_PFR1_EL1 definitions */
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#define ID_PFR1_VIRTEXT_SHIFT 12
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#define ID_PFR1_VIRTEXT_MASK 0xf
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#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
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& ID_PFR1_VIRTEXT_MASK)
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/* SCTLR definitions */
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#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
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(1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
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(1 << 4))
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#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
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2015-07-22 11:53:52 +01:00
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(1 << 20) | (1 << 11))
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2014-09-04 09:23:27 +01:00
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#define SCTLR_AARCH32_EL1_RES1 \
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((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
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(1 << 3))
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2013-10-25 09:08:21 +01:00
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#define SCTLR_M_BIT (1 << 0)
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#define SCTLR_A_BIT (1 << 1)
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#define SCTLR_C_BIT (1 << 2)
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#define SCTLR_SA_BIT (1 << 3)
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#define SCTLR_I_BIT (1 << 12)
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#define SCTLR_WXN_BIT (1 << 19)
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#define SCTLR_EE_BIT (1 << 25)
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/* CPACR_El1 definitions */
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#define CPACR_EL1_FPEN(x) (x << 20)
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#define CPACR_EL1_FP_TRAP_EL0 0x1
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#define CPACR_EL1_FP_TRAP_ALL 0x2
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#define CPACR_EL1_FP_TRAP_NONE 0x3
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/* SCR definitions */
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#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
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#define SCR_TWE_BIT (1 << 13)
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#define SCR_TWI_BIT (1 << 12)
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#define SCR_ST_BIT (1 << 11)
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#define SCR_RW_BIT (1 << 10)
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#define SCR_SIF_BIT (1 << 9)
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#define SCR_HCE_BIT (1 << 8)
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#define SCR_SMD_BIT (1 << 7)
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#define SCR_EA_BIT (1 << 3)
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#define SCR_FIQ_BIT (1 << 2)
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#define SCR_IRQ_BIT (1 << 1)
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#define SCR_NS_BIT (1 << 0)
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2014-05-04 18:38:28 +01:00
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#define SCR_VALID_BIT_MASK 0x2f8f
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2013-10-25 09:08:21 +01:00
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/* HCR definitions */
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#define HCR_RW_BIT (1ull << 31)
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#define HCR_AMO_BIT (1 << 5)
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#define HCR_IMO_BIT (1 << 4)
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#define HCR_FMO_BIT (1 << 3)
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/* CNTHCTL_EL2 definitions */
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2014-06-04 21:10:52 +01:00
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#define EVNTEN_BIT (1 << 2)
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2013-10-25 09:08:21 +01:00
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#define EL1PCEN_BIT (1 << 1)
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#define EL1PCTEN_BIT (1 << 0)
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/* CNTKCTL_EL1 definitions */
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#define EL0PTEN_BIT (1 << 9)
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#define EL0VTEN_BIT (1 << 8)
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#define EL0PCTEN_BIT (1 << 0)
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#define EL0VCTEN_BIT (1 << 1)
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2014-07-17 16:06:39 +01:00
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#define EVNTEN_BIT (1 << 2)
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#define EVNTDIR_BIT (1 << 3)
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#define EVNTI_SHIFT 4
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#define EVNTI_MASK 0xf
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2013-10-25 09:08:21 +01:00
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/* CPTR_EL3 definitions */
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2014-01-14 18:11:48 +00:00
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#define TCPAC_BIT (1 << 31)
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#define TTA_BIT (1 << 20)
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2013-10-25 09:08:21 +01:00
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#define TFP_BIT (1 << 10)
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/* CPSR/SPSR definitions */
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#define DAIF_FIQ_BIT (1 << 0)
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#define DAIF_IRQ_BIT (1 << 1)
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#define DAIF_ABT_BIT (1 << 2)
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#define DAIF_DBG_BIT (1 << 3)
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2014-05-13 14:42:08 +01:00
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#define SPSR_DAIF_SHIFT 6
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#define SPSR_DAIF_MASK 0xf
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#define SPSR_AIF_SHIFT 6
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#define SPSR_AIF_MASK 0x7
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#define SPSR_E_SHIFT 9
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#define SPSR_E_MASK 0x1
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#define SPSR_E_LITTLE 0x0
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#define SPSR_E_BIG 0x1
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#define SPSR_T_SHIFT 5
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#define SPSR_T_MASK 0x1
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#define SPSR_T_ARM 0x0
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#define SPSR_T_THUMB 0x1
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#define DISABLE_ALL_EXCEPTIONS \
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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2013-10-25 09:08:21 +01:00
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/*
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* TCR defintions
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*/
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#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
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2014-06-28 00:56:30 +01:00
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#define TCR_EL1_IPS_SHIFT 32
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#define TCR_EL3_PS_SHIFT 16
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/* (internal) physical address size bits in EL3/EL1 */
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#define TCR_PS_BITS_4GB (0x0)
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#define TCR_PS_BITS_64GB (0x1)
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#define TCR_PS_BITS_1TB (0x2)
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#define TCR_PS_BITS_4TB (0x3)
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#define TCR_PS_BITS_16TB (0x4)
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#define TCR_PS_BITS_256TB (0x5)
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#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL
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#define ADDR_MASK_44_TO_47 0x0000F00000000000UL
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#define ADDR_MASK_42_TO_43 0x00000C0000000000UL
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#define ADDR_MASK_40_TO_41 0x0000030000000000UL
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#define ADDR_MASK_36_TO_39 0x000000F000000000UL
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#define ADDR_MASK_32_TO_35 0x0000000F00000000UL
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2013-10-25 09:08:21 +01:00
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#define TCR_RGN_INNER_NC (0x0 << 8)
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#define TCR_RGN_INNER_WBA (0x1 << 8)
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#define TCR_RGN_INNER_WT (0x2 << 8)
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#define TCR_RGN_INNER_WBNA (0x3 << 8)
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#define TCR_RGN_OUTER_NC (0x0 << 10)
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#define TCR_RGN_OUTER_WBA (0x1 << 10)
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#define TCR_RGN_OUTER_WT (0x2 << 10)
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#define TCR_RGN_OUTER_WBNA (0x3 << 10)
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#define TCR_SH_NON_SHAREABLE (0x0 << 12)
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#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
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#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
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2014-05-13 14:42:08 +01:00
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#define MODE_SP_SHIFT 0x0
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#define MODE_SP_MASK 0x1
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2013-10-25 09:08:21 +01:00
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|
#define MODE_SP_EL0 0x0
|
|
|
|
|
#define MODE_SP_ELX 0x1
|
2014-05-13 14:42:08 +01:00
|
|
|
|
|
|
|
|
#define MODE_RW_SHIFT 0x4
|
|
|
|
|
#define MODE_RW_MASK 0x1
|
|
|
|
|
#define MODE_RW_64 0x0
|
|
|
|
|
#define MODE_RW_32 0x1
|
|
|
|
|
|
|
|
|
|
#define MODE_EL_SHIFT 0x2
|
|
|
|
|
#define MODE_EL_MASK 0x3
|
2013-10-25 09:08:21 +01:00
|
|
|
#define MODE_EL3 0x3
|
|
|
|
|
#define MODE_EL2 0x2
|
|
|
|
|
#define MODE_EL1 0x1
|
|
|
|
|
#define MODE_EL0 0x0
|
|
|
|
|
|
2014-05-13 14:42:08 +01:00
|
|
|
#define MODE32_SHIFT 0
|
|
|
|
|
#define MODE32_MASK 0xf
|
|
|
|
|
#define MODE32_usr 0x0
|
|
|
|
|
#define MODE32_fiq 0x1
|
|
|
|
|
#define MODE32_irq 0x2
|
|
|
|
|
#define MODE32_svc 0x3
|
|
|
|
|
#define MODE32_mon 0x6
|
|
|
|
|
#define MODE32_abt 0x7
|
|
|
|
|
#define MODE32_hyp 0xa
|
|
|
|
|
#define MODE32_und 0xb
|
|
|
|
|
#define MODE32_sys 0xf
|
|
|
|
|
|
|
|
|
|
#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
|
|
|
|
|
#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
|
|
|
|
|
#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
|
|
|
|
|
#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
|
|
|
|
|
|
|
|
|
|
#define SPSR_64(el, sp, daif) \
|
|
|
|
|
(MODE_RW_64 << MODE_RW_SHIFT | \
|
|
|
|
|
((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
|
|
|
|
|
((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
|
|
|
|
|
((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define SPSR_MODE32(mode, isa, endian, aif) \
|
|
|
|
|
(MODE_RW_32 << MODE_RW_SHIFT | \
|
|
|
|
|
((mode) & MODE32_MASK) << MODE32_SHIFT | \
|
|
|
|
|
((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
|
|
|
|
|
((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
|
|
|
|
|
((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
|
2013-10-25 09:08:21 +01:00
|
|
|
|
2015-03-30 17:15:16 +01:00
|
|
|
/*
|
|
|
|
|
* CTR_EL0 definitions
|
|
|
|
|
*/
|
|
|
|
|
#define CTR_CWG_SHIFT 24
|
|
|
|
|
#define CTR_CWG_MASK 0xf
|
|
|
|
|
#define CTR_ERG_SHIFT 20
|
|
|
|
|
#define CTR_ERG_MASK 0xf
|
|
|
|
|
#define CTR_DMINLINE_SHIFT 16
|
|
|
|
|
#define CTR_DMINLINE_MASK 0xf
|
|
|
|
|
#define CTR_L1IP_SHIFT 14
|
|
|
|
|
#define CTR_L1IP_MASK 0x3
|
|
|
|
|
#define CTR_IMINLINE_SHIFT 0
|
|
|
|
|
#define CTR_IMINLINE_MASK 0xf
|
|
|
|
|
|
|
|
|
|
#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
|
|
|
|
|
#define SIZE_FROM_LOG2_WORDS(n) (4 << (n))
|
|
|
|
|
|
2013-10-25 09:08:21 +01:00
|
|
|
|
2014-05-09 12:00:17 +01:00
|
|
|
/* Physical timer control register bit fields shifts and masks */
|
|
|
|
|
#define CNTP_CTL_ENABLE_SHIFT 0
|
|
|
|
|
#define CNTP_CTL_IMASK_SHIFT 1
|
|
|
|
|
#define CNTP_CTL_ISTATUS_SHIFT 2
|
|
|
|
|
|
|
|
|
|
#define CNTP_CTL_ENABLE_MASK 1
|
|
|
|
|
#define CNTP_CTL_IMASK_MASK 1
|
|
|
|
|
#define CNTP_CTL_ISTATUS_MASK 1
|
|
|
|
|
|
|
|
|
|
#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \
|
|
|
|
|
CNTP_CTL_ENABLE_MASK)
|
|
|
|
|
#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \
|
|
|
|
|
CNTP_CTL_IMASK_MASK)
|
|
|
|
|
#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
|
|
|
|
|
CNTP_CTL_ISTATUS_MASK)
|
|
|
|
|
|
|
|
|
|
#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
|
|
|
|
|
#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
|
|
|
|
|
#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
|
|
|
|
|
|
2013-10-25 09:08:21 +01:00
|
|
|
/* Miscellaneous MMU related constants */
|
|
|
|
|
#define NUM_2MB_IN_GB (1 << 9)
|
|
|
|
|
#define NUM_4K_IN_2MB (1 << 9)
|
2014-02-09 13:30:38 +00:00
|
|
|
#define NUM_GB_IN_4GB (1 << 2)
|
2013-10-25 09:08:21 +01:00
|
|
|
|
|
|
|
|
#define TWO_MB_SHIFT 21
|
|
|
|
|
#define ONE_GB_SHIFT 30
|
|
|
|
|
#define FOUR_KB_SHIFT 12
|
|
|
|
|
|
|
|
|
|
#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
|
|
|
|
|
#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
|
|
|
|
|
#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define INVALID_DESC 0x0
|
|
|
|
|
#define BLOCK_DESC 0x1
|
|
|
|
|
#define TABLE_DESC 0x3
|
|
|
|
|
|
|
|
|
|
#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
|
|
|
|
|
#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
|
|
|
|
|
#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
|
|
|
|
|
|
|
|
|
|
#define LEVEL1 1
|
|
|
|
|
#define LEVEL2 2
|
|
|
|
|
#define LEVEL3 3
|
|
|
|
|
|
|
|
|
|
#define XN (1ull << 2)
|
|
|
|
|
#define PXN (1ull << 1)
|
|
|
|
|
#define CONT_HINT (1ull << 0)
|
|
|
|
|
|
|
|
|
|
#define UPPER_ATTRS(x) (x & 0x7) << 52
|
|
|
|
|
#define NON_GLOBAL (1 << 9)
|
|
|
|
|
#define ACCESS_FLAG (1 << 8)
|
|
|
|
|
#define NSH (0x0 << 6)
|
|
|
|
|
#define OSH (0x2 << 6)
|
|
|
|
|
#define ISH (0x3 << 6)
|
|
|
|
|
|
2014-01-24 15:41:33 +00:00
|
|
|
#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
|
|
|
|
|
#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
|
|
|
|
|
#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
|
|
|
|
|
#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
|
|
|
|
|
|
|
|
|
|
#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
|
|
|
|
|
#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
|
|
|
|
|
|
|
|
|
|
#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT
|
|
|
|
|
#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
|
|
|
|
|
|
|
|
|
|
/* Values for number of entries in each MMU translation table */
|
|
|
|
|
#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
|
|
|
|
|
#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
|
|
|
|
|
#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
|
|
|
|
|
|
|
|
|
|
/* Values to convert a memory address to an index into a translation table */
|
|
|
|
|
#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
|
|
|
|
|
#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
|
|
|
|
|
#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
|
2013-11-27 09:38:52 +00:00
|
|
|
|
2013-10-25 09:08:21 +01:00
|
|
|
/*
|
|
|
|
|
* AP[1] bit is ignored by hardware and is
|
|
|
|
|
* treated as if it is One in EL2/EL3
|
|
|
|
|
*/
|
|
|
|
|
#define AP_RO (0x1 << 5)
|
|
|
|
|
#define AP_RW (0x0 << 5)
|
|
|
|
|
|
|
|
|
|
#define NS (0x1 << 3)
|
Extend memory attributes to map non-cacheable memory
At the moment, the memory translation library allows to create memory
mappings of 2 types:
- Device nGnRE memory (named MT_DEVICE in the library);
- Normal, Inner Write-back non-transient, Outer Write-back
non-transient memory (named MT_MEMORY in the library).
As a consequence, the library code treats the memory type field as a
boolean: everything that is not device memory is normal memory and
vice-versa.
In reality, the ARMv8 architecture allows up to 8 types of memory to
be used at a single time for a given exception level. This patch
reworks the memory attributes such that the memory type is now defined
as an integer ranging from 0 to 7 instead of a boolean. This makes it
possible to extend the list of memory types supported by the memory
translation library.
The priority system dictating memory attributes for overlapping
memory regions has been extended to cope with these changes but the
algorithm at its core has been preserved. When a memory region is
re-mapped with different memory attributes, the memory translation
library examines the former attributes and updates them only if
the new attributes create a more restrictive mapping. This behaviour
is unchanged, only the manipulation of the value has been modified
to cope with the new format.
This patch also introduces a new type of memory mapping in the memory
translation library: MT_NON_CACHEABLE, meaning Normal, Inner
Non-cacheable, Outer Non-cacheable memory. This can be useful to map
a non-cacheable memory region, such as a DMA buffer for example.
The rules around the Execute-Never (XN) bit in a translation table
for an MT_NON_CACHEABLE memory mapping have been aligned on the rules
used for MT_MEMORY mappings:
- If the memory is read-only then it is also executable (XN = 0);
- If the memory is read-write then it is not executable (XN = 1).
The shareability field for MT_NON_CACHEABLE mappings is always set as
'Outer-Shareable'. Note that this is not strictly needed since
shareability is only relevant if the memory is a Normal Cacheable
memory type, but this is to align with the existing device memory
mappings setup. All Device and Normal Non-cacheable memory regions
are always treated as Outer Shareable, regardless of the translation
table shareability attributes.
This patch also removes the 'ATTR_SO' and 'ATTR_SO_INDEX' #defines.
They were introduced to map memory as Device nGnRnE (formerly called
"Strongly-Ordered" memory in the ARMv7 architecture) but were not
used anywhere in the code base. Removing them avoids any confusion
about the memory types supported by the library.
Upstream platforms do not currently use the MT_NON_CACHEABLE memory
type.
NOTE: THIS CHANGE IS SOURCE COMPATIBLE BUT PLATFORMS THAT RELY ON THE
BINARY VALUES OF `mmap_attr_t` or the `attr` argument of
`mmap_add_region()` MAY BE BROKEN.
Change-Id: I717d6ed79b4c845a04e34132432f98b93d661d79
2016-03-01 14:01:03 +00:00
|
|
|
#define ATTR_NON_CACHEABLE_INDEX 0x2
|
2013-10-25 09:08:21 +01:00
|
|
|
#define ATTR_DEVICE_INDEX 0x1
|
|
|
|
|
#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
|
|
|
|
|
#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
|
Extend memory attributes to map non-cacheable memory
At the moment, the memory translation library allows to create memory
mappings of 2 types:
- Device nGnRE memory (named MT_DEVICE in the library);
- Normal, Inner Write-back non-transient, Outer Write-back
non-transient memory (named MT_MEMORY in the library).
As a consequence, the library code treats the memory type field as a
boolean: everything that is not device memory is normal memory and
vice-versa.
In reality, the ARMv8 architecture allows up to 8 types of memory to
be used at a single time for a given exception level. This patch
reworks the memory attributes such that the memory type is now defined
as an integer ranging from 0 to 7 instead of a boolean. This makes it
possible to extend the list of memory types supported by the memory
translation library.
The priority system dictating memory attributes for overlapping
memory regions has been extended to cope with these changes but the
algorithm at its core has been preserved. When a memory region is
re-mapped with different memory attributes, the memory translation
library examines the former attributes and updates them only if
the new attributes create a more restrictive mapping. This behaviour
is unchanged, only the manipulation of the value has been modified
to cope with the new format.
This patch also introduces a new type of memory mapping in the memory
translation library: MT_NON_CACHEABLE, meaning Normal, Inner
Non-cacheable, Outer Non-cacheable memory. This can be useful to map
a non-cacheable memory region, such as a DMA buffer for example.
The rules around the Execute-Never (XN) bit in a translation table
for an MT_NON_CACHEABLE memory mapping have been aligned on the rules
used for MT_MEMORY mappings:
- If the memory is read-only then it is also executable (XN = 0);
- If the memory is read-write then it is not executable (XN = 1).
The shareability field for MT_NON_CACHEABLE mappings is always set as
'Outer-Shareable'. Note that this is not strictly needed since
shareability is only relevant if the memory is a Normal Cacheable
memory type, but this is to align with the existing device memory
mappings setup. All Device and Normal Non-cacheable memory regions
are always treated as Outer Shareable, regardless of the translation
table shareability attributes.
This patch also removes the 'ATTR_SO' and 'ATTR_SO_INDEX' #defines.
They were introduced to map memory as Device nGnRnE (formerly called
"Strongly-Ordered" memory in the ARMv7 architecture) but were not
used anywhere in the code base. Removing them avoids any confusion
about the memory types supported by the library.
Upstream platforms do not currently use the MT_NON_CACHEABLE memory
type.
NOTE: THIS CHANGE IS SOURCE COMPATIBLE BUT PLATFORMS THAT RELY ON THE
BINARY VALUES OF `mmap_attr_t` or the `attr` argument of
`mmap_add_region()` MAY BE BROKEN.
Change-Id: I717d6ed79b4c845a04e34132432f98b93d661d79
2016-03-01 14:01:03 +00:00
|
|
|
#define ATTR_NON_CACHEABLE (0x44)
|
2013-10-25 09:08:21 +01:00
|
|
|
#define ATTR_DEVICE (0x4)
|
|
|
|
|
#define ATTR_IWBWA_OWBWA_NTR (0xff)
|
|
|
|
|
#define MAIR_ATTR_SET(attr, index) (attr << (index << 3))
|
|
|
|
|
|
|
|
|
|
/* Exception Syndrome register bits and bobs */
|
|
|
|
|
#define ESR_EC_SHIFT 26
|
|
|
|
|
#define ESR_EC_MASK 0x3f
|
|
|
|
|
#define ESR_EC_LENGTH 6
|
|
|
|
|
#define EC_UNKNOWN 0x0
|
|
|
|
|
#define EC_WFE_WFI 0x1
|
|
|
|
|
#define EC_AARCH32_CP15_MRC_MCR 0x3
|
|
|
|
|
#define EC_AARCH32_CP15_MRRC_MCRR 0x4
|
|
|
|
|
#define EC_AARCH32_CP14_MRC_MCR 0x5
|
|
|
|
|
#define EC_AARCH32_CP14_LDC_STC 0x6
|
|
|
|
|
#define EC_FP_SIMD 0x7
|
|
|
|
|
#define EC_AARCH32_CP10_MRC 0x8
|
|
|
|
|
#define EC_AARCH32_CP14_MRRC_MCRR 0xc
|
|
|
|
|
#define EC_ILLEGAL 0xe
|
|
|
|
|
#define EC_AARCH32_SVC 0x11
|
|
|
|
|
#define EC_AARCH32_HVC 0x12
|
|
|
|
|
#define EC_AARCH32_SMC 0x13
|
|
|
|
|
#define EC_AARCH64_SVC 0x15
|
|
|
|
|
#define EC_AARCH64_HVC 0x16
|
|
|
|
|
#define EC_AARCH64_SMC 0x17
|
|
|
|
|
#define EC_AARCH64_SYS 0x18
|
|
|
|
|
#define EC_IABORT_LOWER_EL 0x20
|
|
|
|
|
#define EC_IABORT_CUR_EL 0x21
|
|
|
|
|
#define EC_PC_ALIGN 0x22
|
|
|
|
|
#define EC_DABORT_LOWER_EL 0x24
|
|
|
|
|
#define EC_DABORT_CUR_EL 0x25
|
|
|
|
|
#define EC_SP_ALIGN 0x26
|
|
|
|
|
#define EC_AARCH32_FP 0x28
|
|
|
|
|
#define EC_AARCH64_FP 0x2c
|
|
|
|
|
#define EC_SERROR 0x2f
|
|
|
|
|
|
|
|
|
|
#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
|
|
|
|
|
|
2014-05-14 17:44:19 +01:00
|
|
|
/*******************************************************************************
|
|
|
|
|
* Definitions of register offsets and fields in the CNTCTLBase Frame of the
|
|
|
|
|
* system level implementation of the Generic Timer.
|
|
|
|
|
******************************************************************************/
|
|
|
|
|
#define CNTNSAR 0x4
|
|
|
|
|
#define CNTNSAR_NS_SHIFT(x) x
|
|
|
|
|
|
|
|
|
|
#define CNTACR_BASE(x) (0x40 + (x << 2))
|
|
|
|
|
#define CNTACR_RPCT_SHIFT 0x0
|
|
|
|
|
#define CNTACR_RVCT_SHIFT 0x1
|
|
|
|
|
#define CNTACR_RFRQ_SHIFT 0x2
|
|
|
|
|
#define CNTACR_RVOFF_SHIFT 0x3
|
|
|
|
|
#define CNTACR_RWVT_SHIFT 0x4
|
|
|
|
|
#define CNTACR_RWPT_SHIFT 0x5
|
|
|
|
|
|
2013-10-25 09:08:21 +01:00
|
|
|
#endif /* __ARCH_H__ */
|
