Commit Graph

4055 Commits

Author SHA1 Message Date
Rajan Vaja 1ba2d84fe2 xilinx: versal: Updated Response of QueryData API call
For the current XilPM calls, The handler of IPI returns information
with 16 Bytes data.
So during QueryData API call for the ClockName and PinFunctionName,
response data(name of clock or function) response[0..3] are used to
return name. And status is not being returned for such API.

Updated XilPM calls reply in a consistent way and The handler of IPI
return information with 32Bytes data. Where response[0] always set
to status.
For the version-2 of QueryData API, during call for the ClockName
and PinFunctionName, response data(name of clock or function) get as
response[1...4].

To support both the version of QueryData API, added version based
compatibility by the use of feature check.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I336128bff7bbe659903b0f8ce20ae6da7e3b51b4
2020-12-07 11:09:56 +00:00
Venkatesh Yadav Abbarapu abf27efac6 plat:xilinx:versal: Use defaults when PDI is without sw partitions
In JTAG mode check the ATF handoff structure, if the magic string
is not present then use bl32 and bl33 default values.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I1f2c4a2060d8a2e70d3b5fb2473124b685f257fc
2020-12-07 11:09:47 +00:00
Ravi Patel addc4e969b plat: xilinx: Mask unnecessary bytes of return error code
Versal firmware adds extra error codes along with PM error codes
while sending response to driver. This makes incorrect error
identification at driver side.

To fix this, mask the unnecessary error bytes before sending the
error code to the driver.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I18c2f3bd2d067e91344852c2f0c1bafea0e6eb23
2020-12-07 11:08:09 +00:00
Ravi Patel d4c7b55050 xilinx: versal: Skip store/restore of GIC during CPU idle
GIC registers needs to be stored/restored during system
suspend/resume only and not during CPU idle.
During CPU idle, minimum 1 CPU is in ON state.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I5de2ce3a61bf4260f9385349202b0f592a47aaba
2020-12-07 11:07:41 +00:00
Venkatesh Yadav Abbarapu 4b8ab607ea plat: versal: Update API list in feature check
Add below API in feature check list which is actually present in
firmware:
- PM_GET_CHIPID

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98b82da74164f065c8835861f74b0f2855e9bcbf
2020-12-07 11:07:32 +00:00
Ravi Patel b05d2792ae xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()
Existing code passes ACPU0 to LibPM as node_id in set_wakeup_source()
call because last suspending core will be ACPU0 in most of the case.

Now it may be possible that user may disable the ACPU0 using hot-plug
and after that it suspends Linux. So in that case ACPU0 will not be
last suspending core.

To overcome above scenario, pass the current running processor ID
while calling set_wakeup_source().

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If15354c2150b5bb1305b5f93ca4e8c7a81d59f0a
2020-12-07 11:07:24 +00:00
Madhukar Pappireddy 7fc19b8ea9 Merge "qemu/qemu_sbsa: increase SHARED_RAM_SIZE" into integration 2020-12-07 03:40:39 +00:00
Venkatesh Yadav Abbarapu 84f2e34fee plat: xilinx: zynqmp: Include GICv2 makefile
Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done in the commit #1322dc94f7.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8
2020-12-03 20:30:37 -07:00
Madhukar Pappireddy 79df6ea430 Merge "plat: xilinx: Use fno-jump-tables flag in CPPFLAGS" into integration 2020-12-03 16:58:59 +00:00
Madhukar Pappireddy 5e5c399de0 Merge "plat: marvell: Update SUBVERSION to match Marvell's forked version" into integration 2020-12-03 15:51:50 +00:00
Madhukar Pappireddy 0888694076 Merge "rockchip: Add support for the stack protector" into integration 2020-12-02 18:26:47 +00:00
Lauren Wehrmeister 9dd2896e65 Merge "Add support for Neoverse-N2 CPUs." into integration 2020-12-01 17:06:46 +00:00
Masato Fukumori 54b590ec0d qemu/qemu_sbsa: increase SHARED_RAM_SIZE
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.

sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured with 512 cpus, region size used by qemu is greater
than 4KB.

Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org>
Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
2020-12-01 14:01:24 +00:00
Christoph Müllner 826ba363c4 rockchip: Add support for the stack protector
It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signed-off-by: Christoph Müllner <christophm30@gmail.com>
2020-12-01 11:54:57 +01:00
Javier Almansa Sobrino 25bbbd2d63 Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-11-30 19:12:56 +00:00
Manish Pandey 9acf573621 Merge changes from topic "xilinx-pm-mainline-linux" into integration
* changes:
  zynqmp: pm: update error codes to match Linux and PMU Firmware
  zynqmp: pm: Filter errors related to clock gate permissions
2020-11-30 12:05:11 +00:00
Manish Pandey 441e7f489f Merge "mediatek: mt8183: add timer V20 compensation" into integration 2020-11-27 11:11:39 +00:00
Manish Pandey 9272a8fd7b Merge "plat:qti Mandate SMC implementaion" into integration 2020-11-23 10:29:48 +00:00
Madhukar Pappireddy 7cf307d209 Merge "plat/nvidia: tegra: Rename SMC API" into integration 2020-11-20 15:36:37 +00:00
Tanmay Jagdale 5f14ca9937 plat/qemu_sbsa: Include libraries for Cortex-A72
Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba
2020-11-20 16:39:49 +05:30
Manish V Badarkhe 840fa94aa3 plat/nvidia: tegra: Rename SMC API
Renamed SMC API from "plat_smccc_feature_available" to
"plat_is_smccc_feature_available" as per the current implementation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib0fa400816fba61039c2029a9e127501a6a36811
2020-11-19 20:09:28 +00:00
Saurabh Gorecha 7a0f795ee7 plat:qti Mandate SMC implementaion
renamed smcc api with correct name  plat_is_smccc_feature_available

Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
2020-11-20 01:09:52 +05:30
Pali Rohár d22db1b050 plat: marvell: Update SUBVERSION to match Marvell's forked version
Marvell's TF-A fork has SUBVERSION set to devel-18.12.2.

The only differences between Marvell's devel-18.12.0 and devel-18.12.2
versions are documentation updates and cherry-picked patches from TF-A
upstream repository.

So upstream TF-A has already all changes from Marvell's TF-A devel-18.12.2
fork and therefore update SUBVERSION to reflect this state.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ce946a5176a5cbf124acd8037392463d586b072
2020-11-19 10:17:39 +00:00
Pali Rohár 91bc2da73c plat: marvell: armada: Add new target mrvl_bootimage
This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository is not
required for building.

Having ability to build just this boot-image.bin binary without full
flash-image.bin is useful for A3720 Turris MOX board which does not use
Marvell's WTP and a3700_utils.

To reduce duplicity between a8k and a3k code, define this new target and
also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file
marvell_common.mk.

For this purpose it is needed to include plat/marvell/marvell.mk file from
a3700_common.mk unconditionally (and not only when WTP is defined). Now
when common file plat/marvell/marvell.mk does not contain definition for
building $(DOIMAGETOOL), it is possible to move its inclusion at the top of
the a3700_common.mk file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
2020-11-19 10:17:28 +00:00
Pali Rohár c6a7ab7787 plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)
Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL)
variable points to external pre-compiled Marvell x86_64 ELF linux binary
from A3700-utils-marvell WTP repository.

It means that currently it is not possible to compile TF-A for A3720 on
other host platform then linux x86_64.

Part of the A3700-utils-marvell WTP repository is also source code of
$(DOIMAGETOOL) TBB_Linux tool.

This change adds support for building $(DOIMAGETOOL) also for a3k platform.

After running $(MAKE) at appropriate subdirectory of A3700-utils-marvell
WTP repository, compiled TBB_linux tool will appear in WTP subdirectory
wtptp/src/TBB_Linux/release/. So update also $(DOIMAGETOOL) variable to
point to the correct location where TBB_linux was built.

To build TBB_linux it is required to compile external Crypto++ library
which is available at: https://github.com/weidai11/cryptopp.git

User needs to set CRYPTOPP_PATH option to specify path to that library.

After this change it is now possible to build whole firmware for A3720
platform without requirement to use pre-compiled/proprietary x86_64
executable binaries from Marvell.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6f26bd4356778a2f8f730a223067a2e550e6c8e0
2020-11-19 10:17:21 +00:00
David Horstmann 5d9101b39c Fix typos and misspellings
Fix a number of typos and misspellings in TF-A
documentation and comments.

Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee
2020-11-12 15:21:11 +00:00
Venkatesh Yadav Abbarapu e9930d42c7 plat: xilinx: Use fno-jump-tables flag in CPPFLAGS
From GCC-9 implementation of switch case was generated through jump tables,
because of which we are seeing 1MB increase in rodata section. To reduce
the size we are recommending to use fno-jump-tables.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I069733610809b8299fbf641f0ae35b359a8afd69
2020-11-12 10:40:16 +01:00
Davorin Mista a8b10c6490 zynqmp: pm: update error codes to match Linux and PMU Firmware
All EEMI error codes start with value 2000.

Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by
current ATF code have been left in place.

Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6
2020-11-12 10:27:14 +01:00
Mirela Simonovic c23cf05303 zynqmp: pm: Filter errors related to clock gate permissions
Linux clock framework cannot properly deal with these errors. When the
error is related to the lack of permissions to control the clock we
filter the error and report the success to linux. Before recent changes
in clock framework across the stack, this was done in the PMU-FW as a
workaround. Since the PMU-FW now handles clocks and the permissions to
control them using general principles rather than workarounds, it can
no longer distinguish such exceptions and it has to return no-access
error.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I1491a80e472f44e322a542b29a20eb1cb3319802
2020-11-12 10:26:57 +01:00
Alexei Fedorov 8109d2dd69 Merge "Use constant stack size with RECLAIM_INIT_CODE" into integration 2020-10-29 18:00:13 +00:00
Manish Pandey 271708e064 Merge changes from topic "mbox-patches" into integration
* changes:
  intel: common: Fix non-MISRA compliant code v2
  intel: mailbox: Fix non-MISRA compliant code
  intel: mailbox: Mailbox error recovery handling
  intel: mailbox: Enable sending large mailbox command
  intel: mailbox: Use retry count in mailbox poll
  intel: mailbox: Ensure time out duration is predictive
  intel: mailbox: Read mailbox response even there is an error
  intel: mailbox: Driver now handles larger response
  intel: common: Change how mailbox handles job id & buffer
  intel: common: Improve readability of mailbox read response
  intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
  intel: common: Remove urgent from mailbox async
  intel: common: Improve mailbox driver readability
2020-10-29 11:17:01 +00:00
David Horstmann 3ed5606bd1 Use constant stack size with RECLAIM_INIT_CODE
Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes an issue in lib/psci/aarch64/psci_helpers.S,
where the stack size is used for cache operations in
psci_do_pwrdown_cache_maintenance(). If the stacks
are scaled, then the PSCI code may fail to invalidate
some of the stack memory before power down.

Resizing stacks is also not good for stability in general,
since code that works with a small number of cores may
overflow the stack when the number of cores is increased.

Change to make every stack be PLATFORM_STACK_SIZE big,
and allow the total stack to be smaller than the
init section.

Any pages of the init section not reclaimed as
stack will be set to read-only and execute-never,
for security.

Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8
Signed-off-by: David Horstmann <david.horstmann@arm.com>
2020-10-28 17:58:49 +00:00
Manish Pandey 6e97b22456 Merge changes from topic "mbox-patches" into integration
* changes:
  intel: common: Clean up mailbox and sip header
  intel: clear 'PLAT_SEC_ENTRY' in early platform setup
2020-10-28 14:07:15 +00:00
Manish Pandey 350c04f6c1 Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration
* changes:
  mediatek: mt8192: add timer support
  mediatek: mt8192: Add reboot function for PSCI
  mediatek: mt8192: add sys_cirq driver
  mediatek: mt8192: add GPIO driver support
2020-10-28 14:04:07 +00:00
Dehui Sun 4a128018b6 mediatek: mt8192: add timer support
add timer driver.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7
2020-10-28 17:21:55 +08:00
Nina Wu 0f40824729 mediatek: mt8192: Add reboot function for PSCI
Add system_reset function in psci ops

Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-10-28 17:21:55 +08:00
gtk_pangao b6cec33785 mediatek: mt8192: add sys_cirq driver
1.add sys_cirq driver
2.add gic api for cirq

Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
2020-10-28 17:21:55 +08:00
Manish Pandey c03657051e Merge "plat: marvell: armada: Fix dependences for target fip" into integration 2020-10-27 14:01:11 +00:00
Abdul Halim, Muhammad Hadi Asyrafi d57318b7c9 intel: common: Fix non-MISRA compliant code v2
This patch is used to fix remaining non compliant code for Intel
SoCFPGA's mailbox and sip driver. These changes include:
- Change non-interface required uint32_t into unsigned int
- Change non-negative variable to unsigned int
- Remove obsolete variable initialization to 0

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5
2020-10-27 11:21:00 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 9e285909ae intel: mailbox: Fix non-MISRA compliant code
This patch is used to fix remaining non compliant code for Intel
SocFPGA's mailbox driver. These changes include:
- adding integer literal for unsigned constant
- fix non-boolean controlling expression
- add braces even on conditional single statement bodies

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1
2020-10-27 11:20:59 +08:00
Chee Hong Ang 997560470a intel: mailbox: Mailbox error recovery handling
Attempt to restart the mailbox if the mailbox driver not able
to write any data into the mailbox command buffer.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: Ia45291c985844dec9da82839cac701347534d32b
2020-10-27 11:20:59 +08:00
Abdul Halim, Muhammad Hadi Asyrafi d14e965c03 intel: mailbox: Enable sending large mailbox command
Allow mailbox command that is larger than mailbox command FIFO buffer
size to be sent to SDM in multiple chunks.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26
2020-10-27 11:20:55 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 4978bc2832 intel: mailbox: Use retry count in mailbox poll
Change the main loop inside mailbox poll function from while(1) to a
retry counter named sdm_loop. This is to limit the maximum possible
looping of the function and prevent unexpected behaviour.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d
2020-10-27 11:17:41 +08:00
Chee Hong Ang d96e7cda8a intel: mailbox: Ensure time out duration is predictive
For each count down of time out counter, wait for number of
miliseconds to ensure the time out duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b
2020-10-27 11:17:40 +08:00
Chee Hong Ang 6d9f9f5ea0 intel: mailbox: Read mailbox response even there is an error
Mailbox driver should read the response data if the response length
in the response header is non-zero even the response header indicates
error (non-zero).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640
2020-10-27 11:17:40 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 39aebd358e intel: mailbox: Driver now handles larger response
This patch factorizes mailbox read response from SDM into a function.
Also fix the logic to support reading larger than 16 words response from
SDM.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5
2020-10-27 11:17:40 +08:00
Abdul Halim, Muhammad Hadi Asyrafi aad868b4d9 intel: common: Change how mailbox handles job id & buffer
This patch modifies several basic mailbox driver features to prepare for
FCS enablement:
- Job id management for asynchronous response
- SDM command buffer full

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2
2020-10-27 11:17:34 +08:00
Olivier Deprez 00ad74c7af Merge "SPMC: adjust device region for first secure partition" into integration 2020-10-26 09:51:32 +00:00
Po Xu 054af8f233 mediatek: mt8192: add GPIO driver support
add GPIO driver

Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
2020-10-26 16:21:11 +08:00
Abdul Halim, Muhammad Hadi Asyrafi 516f32219b intel: common: Clean up mailbox and sip header
Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856
2020-10-24 11:00:42 +08:00