Commit Graph

833 Commits

Author SHA1 Message Date
Sandrine Bailleux 21c4f56fa7 Merge changes from topic "lm/fconf" into integration
* changes:
  arm-io: Panic in case of io setup failure
  MISRA fix: Use boolean essential type
  fconf: Add documentation
  fconf: Move platform io policies into fconf
  fconf: Add mbedtls shared heap as property
  fconf: Add TBBR disable_authentication property
  fconf: Add dynamic config DTBs info as property
  fconf: Populate properties from dtb during bl2 setup
  fconf: Load config dtb from bl1
  fconf: initial commit
2020-02-11 16:15:45 +00:00
Louis Mayencourt 6c97231760 fconf: Add mbedtls shared heap as property
Use the firmware configuration framework in arm dynamic configuration
to retrieve mbedtls heap information between bl1 and bl2.

For this, a new fconf getter is added to expose the device tree base
address and size.

Change-Id: Ifa5ac9366ae100e2cdd1f4c8e85fc591b170f4b6
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:51:32 +00:00
Louis Mayencourt ce8528411a fconf: Add TBBR disable_authentication property
Use fconf to retrieve the `disable_authentication` property.
Move this access from arm dynamic configuration to bl common.

Change-Id: Ibf184a5c6245d04839222f5457cf5e651f252b86
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:51:32 +00:00
Louis Mayencourt 25ac87940c fconf: Add dynamic config DTBs info as property
This patch introduces a better separation between the trusted-boot
related properties, and the dynamic configuration DTBs loading
information.

The dynamic configuration DTBs properties are moved to a new node:
`dtb-registry`. All the sub-nodes present will be provided to the
dynamic config framework to be loaded. The node currently only contains
the already defined configuration DTBs, but can be extended for future
features if necessary.
The dynamic config framework is modified to use the abstraction provided
by the fconf framework, instead of directly accessing the DTBs.

The trusted-boot properties are kept under the "arm,tb_fw" compatible
string, but in a separate `tb_fw-config` node.
The `tb_fw-config` property of the `dtb-registry` node simply points
to the load address of `fw_config`, as the `tb_fw-config` is currently
part of the same DTB.

Change-Id: Iceb6c4c2cb92b692b6e28dbdc9fb060f1c46de82
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:51:32 +00:00
Louis Mayencourt 9814bfc1bf fconf: Populate properties from dtb during bl2 setup
Use the dtb provided by bl1 as configuration file for fconf.

Change-Id: I3f466ad9b7047e1a361d94e71ac6d693e31496d9
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:51:31 +00:00
Louis Mayencourt 3b5ea741fd fconf: Load config dtb from bl1
Move the loading of the dtb from arm_dym_cfg to fconf. The new loading
function is not associated to arm platform anymore, and can be moved
to bl_main if wanted.

Change-Id: I847d07eaba36d31d9d3ed9eba8e58666ea1ba563
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:48:47 +00:00
Louis Mayencourt ab1981db9e fconf: initial commit
Introduce the Firmware CONfiguration Framework (fconf).

The fconf is an abstraction layer for platform specific data, allowing
a "property" to be queried and a value retrieved without the requesting
entity knowing what backing store is being used to hold the data.

The default backing store used is C structure. If another backing store
has to be used, the platform integrator needs to provide a "populate()"
function to fill the corresponding C structure.
The "populate()" function must be registered to the fconf framework with
the "FCONF_REGISTER_POPULATOR()". This ensures that the function would
be called inside the "fconf_populate()" function.

A two level macro is used as getter:
- the first macro takes 3 parameters and converts it to a function
  call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c).
- the second level defines a__b_getter(c) to the matching C structure,
  variable, array, function, etc..

Ex: Get a Chain of trust property:
    1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id)
    2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id]

Change-Id: Id394001353ed295bc680c3f543af0cf8da549469
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-02-07 13:29:09 +00:00
Zelalem 466bb285c6 coverity: Fix MISRA null pointer violations
Fix code that violates the MISRA rule:
MISRA C-2012 Rule 11.9: Literal "0" shall not be used as
null pointer constant.

The fix explicitly checks whether a pointer is NULL.

Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-05 14:53:02 -06:00
Mark Dykes 235c8174ff Merge "Coverity: remove unnecessary header file includes" into integration 2020-02-04 17:15:57 +00:00
Sandrine Bailleux 9eac8e958e Merge changes from topic "mp/separate_nobits" into integration
* changes:
  plat/arm: Add support for SEPARATE_NOBITS_REGION
  Changes necessary to support SEPARATE_NOBITS_REGION feature
2020-02-04 16:37:09 +00:00
Zelalem e6937287e4 Coverity: remove unnecessary header file includes
This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-04 10:23:51 -06:00
Olivier Deprez 47939f6725 coverity: debugfs devfip remove comparisons to LONG_MAX
CID 353228:  Integer handling issues  (CONSTANT_EXPRESSION_RESULT)

The checks on size and offset_address in get_entry always resolve to
false provided those fields are long long int and cannot be greater
than LONG_MAX.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0fac485a39ac4a40ae8c0d25a706ad74c795e130
2020-02-04 13:40:30 +00:00
Manish Pandey 5f62213e68 Merge "FDT wrappers: add functions for read/write bytes" into integration 2020-02-03 13:45:47 +00:00
Alexei Fedorov 0a2ab6e635 FDT wrappers: add functions for read/write bytes
This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes'
functions for read/write array of bytes from/to a given property.
It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i
files for builds with USE_ROMLIB=1 option.

Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-02-03 11:41:27 +00:00
Alexei Fedorov f69a5828b7 Merge "Use correct type when reading SCR register" into integration 2020-01-30 16:55:55 +00:00
Soby Mathew b1d810bd21 Merge "qemu: Implement PSCI_CPU_OFF." into integration 2020-01-29 15:36:30 +00:00
Soby Mathew 458dde3c44 Merge "T589: Fix insufficient ordering guarantees in bakery lock" into integration 2020-01-29 15:35:23 +00:00
Andrew Walbran 33e8c56973 qemu: Implement PSCI_CPU_OFF.
This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
2020-01-29 10:50:25 +00:00
Soby Mathew 8efec9e097 Merge changes I0fb7cf79,Ia8eb4710 into integration
* changes:
  qemu: Implement qemu_system_off via semihosting.
  qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
2020-01-29 09:51:21 +00:00
Louis Mayencourt f1be00da0b Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-01-28 11:10:48 +00:00
Madhukar Pappireddy c367b75e85 Changes necessary to support SEPARATE_NOBITS_REGION feature
Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.

1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.

2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.

Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-27 15:33:24 -06:00
Raghu Krishnamurthy c0018913b4 T589: Fix insufficient ordering guarantees in bakery lock
bakery_lock_get() uses DMB LD after lock acquisition and
bakery_lock_release() uses DMB ST before releasing the lock. This is
insufficient in both cases. With just DMB LD, stores in the critical
section can be reordered before the DMB LD which could mean writes in
the critical section completing before the lock has been acquired
successfully. Similarly, with just DMB ST, a load in the critical section
could be reordered after the the DMB ST. DMB is the least expensive
barrier that can provide the required ordering.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e
2020-01-27 09:31:31 -08:00
Manish Pandey f2d6b4ee57 Neovers N1: added support to update presence of External LLC
CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.

To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363
2020-01-27 14:44:35 +00:00
Soby Mathew 064d3f6418 Merge "xlat_tables_v2: simplify end address checks in mmap_add_region_check()" into integration 2020-01-24 12:53:18 +00:00
Soby Mathew 5f3ed6aaed Merge "Prevent speculative execution past ERET" into integration 2020-01-24 10:04:10 +00:00
Mark Dykes 4302e045fd Merge "Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"" into integration 2020-01-23 16:11:27 +00:00
laurenw-arm dbafda7cda Errata workarounds N1 1043202, 1315703 default off
Setting errata workarounds for N1 1043202 and 1315703 to 0 since
they should be turned off by default.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9
2020-01-23 10:57:53 +00:00
Andrew Walbran 61cbd41d79 qemu: Implement qemu_system_off via semihosting.
This makes the PSCI SYSTEM_OFF call work on QEMU. It assumes that QEMU has
semihosting enabled, but that is already assumed by the image loader.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I0fb7cf7909262b675c3143efeac07f4d60730b03
2020-01-23 10:53:45 +00:00
Mark Dykes 3b5454efac Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"
This reverts commit 76d84cbc60.

Change-Id: I867af7af3d9f5e568101f79b9ebea578e5cb2a4b
2020-01-22 21:52:44 +00:00
Anthony Steinhauser f461fe346b Prevent speculative execution past ERET
Even though ERET always causes a jump to another address, aarch64 CPUs
speculatively execute following instructions as if the ERET
instruction was not a jump instruction.
The speculative execution does not cross privilege-levels (to the jump
target as one would expect), but it continues on the kernel privilege
level as if the ERET instruction did not change the control flow -
thus execution anything that is accidentally linked after the ERET
instruction. Later, the results of this speculative execution are
always architecturally discarded, however they can leak data using
microarchitectural side channels. This speculative execution is very
reliable (seems to be unconditional) and it manages to complete even
relatively performance-heavy operations (e.g. multiple dependent
fetches from uncached memory).

This was fixed in Linux, FreeBSD, OpenBSD and Optee OS:
679db70801
29fb48ace4
3a08873ece
abfd092aa1

It is demonstrated in a SafeSide example:
https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc
https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c

Signed-off-by: Anthony Steinhauser <asteinhauser@google.com>
Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
2020-01-22 21:42:51 +00:00
Masahiro Yamada c3fc368a5a xlat_tables_v2: simplify end address checks in mmap_add_region_check()
Use end_va and end_pa defined at the beginning of this function.

Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-22 18:35:43 +09:00
Madhukar Pappireddy 76d84cbc60 Changes necessary to support SEPARATE_NOBITS_REGION feature
Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.

1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.

2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.

Change-Id: Ic745c5a130fe4239fa2742142d083b2bdc4e8b85
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-21 19:24:18 -06:00
Lionel Debieve 162fc183cf compiler_rt: Import popcountdi2.c and popcountsi2.c files
Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).

This is to get the __popcountsi2(si_int a) and __popcountdi2(di_int a)
builtin which are required by a driver that uses a __builtin_popcount().

Change-Id: I8e0d97cebdd90d224690c8ce1b02e657acdddb25
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2020-01-20 11:32:59 +01:00
Soby Mathew 45cc606ea7 Merge changes from topic "ld/mtd_framework" into integration
* changes:
  io: change seek offset to signed long long
  compiler_rt: Import aeabi_ldivmode.S file and dependencies
2020-01-17 17:41:21 +00:00
Deepika Bhavnani 5b33ad174a Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
   API `plat_psci_stat_get_residency()` third argument
   `last_cpu_idx` is changed from "signed int" to the
   "unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
2020-01-10 17:11:51 +00:00
Lionel Debieve 8c80c86573 compiler_rt: Import aeabi_ldivmode.S file and dependencies
Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the
LLVM compiler_rt library on master branch as of 30 Oct 2018
(SVN revision: r345645).

This is to get the __aeabi_ldivmod builtin, which is required
by a patch using signed long long division.

Change-Id: Iee4c421deb3175142655e19074cd3732edd82227
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2020-01-02 11:56:07 +01:00
Madhukar Pappireddy 83e955241a Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-12-23 11:21:16 -06:00
Mark Dykes 86ed8953b5 Merge "debugfs: add SMC channel" into integration 2019-12-20 20:56:23 +00:00
Mark Dykes e757b5ee1a Merge "debugfs: add FIP device" into integration 2019-12-20 20:53:28 +00:00
Mark Dykes be84a5b9af Merge "debugfs: add 9p device interface" into integration 2019-12-20 18:10:50 +00:00
Paul Beesley 538b002046 spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.

This patch removes:

- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions

Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
2019-12-20 16:03:32 +00:00
Ambroise Vincent 992f091b5d debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.

Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
2019-12-18 09:59:12 +01:00
Jan Dabros bb9549babc aarch64: Fix stack pointer maintenance on EA handling path
EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
resulted in el3_exit setting runtime stack to context. This in turn
caused memory corruption on consecutive EL3 entries.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0424245c27c369c864506f4baa719968890ce659
2019-12-18 08:47:10 +01:00
Olivier Deprez d310239d77 debugfs: add FIP device
Add a FIP driver hooked to debugfs 9p interface. This is an
abstraction of the FIP filesystem layer on top of a mass storage,
or memory block driver.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If275ea0824763de43ab666dab2a06de5352ff940
2019-12-17 11:06:15 +01:00
Olivier Deprez 0ca3913dd8 debugfs: add 9p device interface
The 9p interface provides abstraction layers allowing the software
that uses devices to be independent from the hardware.

This patch provides a file system abstraction to link drivers to their
devices and propose a common interface to expose driver operations to
higher layers. This file system can be used to access and configure a
device by doing read/write operations.

Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255
2019-12-17 11:03:23 +01:00
Olivier Deprez 2bcc672f34 Merge changes from topic "aa/sel2_support" into integration
* changes:
  S-EL2 Support: Check for AArch64
  Add support for enabling S-EL2
2019-12-13 16:26:32 +00:00
Alexei Fedorov fcccd358e4 Merge "libc: add memrchr" into integration 2019-12-11 10:14:13 +00:00
Ambroise Vincent ebff107268 libc: add memrchr
This function scans a string backwards from the end for the first
instance of a character.

Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-12-11 08:51:26 +01:00
Artsem Artsemenka db3ae8538b S-EL2 Support: Check for AArch64
Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7
2019-12-06 17:42:45 +00:00
Achin Gupta 0376e7c4aa Add support for enabling S-EL2
This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
responsibility to check if S-EL2 is available on the system before requesting
this EL through the entry point information.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1
2019-12-06 17:42:45 +00:00