Commit Graph

6642 Commits

Author SHA1 Message Date
Masahiro Yamada 43bbac27dc uniphier: change the return value type of .is_usb_boot() to bool
This is boolean logic, so "bool" is more suitable.

Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-12 13:36:58 +09:00
Mark Dykes fa764c865d Merge "xilinx: versal: Pass result count to pm_get_callbackdata()" into integration 2020-02-06 20:44:38 +00:00
Mark Dykes bdcc45a744 Merge "plat: xilinx: zynqmp: Use ARRAY_SIZE wherever possible" into integration 2020-02-06 20:43:58 +00:00
György Szing cf96f2ed03 Merge "doc: Split and expand coding style documentation" into integration 2020-02-06 16:31:23 +00:00
Paul Beesley e63f5d129f doc: Split and expand coding style documentation
This patch expands the coding style documentation, splitting it
into two documents: the core style rules and extended guidelines.
Note that it does not redefine or change the coding style (aside
from section 4.6.2) - generally, it is only documenting the
existing style in more detail.

The aim is for the coding style to be more readable and, in turn,
for it to be followed by more people. We can use this as a more
concrete reference when discussing the accepted style with external
contributors.

Change-Id: I87405ace9a879d7f81e6b0b91b93ca69535e50ff
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
2020-02-06 16:25:06 +00:00
György Szing 3a415eb9d1 Merge "doc: Remove backquotes from external hyperlinks" into integration 2020-02-06 12:10:52 +00:00
Mark Dykes 378206e909 Merge "Tegra194: mce: declare nvg_roc_clean_cache_trbits()" into integration 2020-02-05 20:53:29 +00:00
Varun Wadekar bf14df1e97 Tegra194: mce: declare nvg_roc_clean_cache_trbits()
This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

Change-Id: I313556f6799792fc0141afb5822cc157db80bc47
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-02-05 19:15:40 +00:00
Manish Pandey ac89345649 Merge changes from topic "tegra-downstream-01242020" into integration
* changes:
  Tegra186: memctrl: lock stream id security config
  Tegra194: remove support for simulated system suspend
  Tegra194: mce: fix multiple MISRA issues
  Tegra: bpmp: fix multiple MISRA issues
  Tegra194: se: fix multiple MISRA issues
  Tegra: compile PMC driver for Tegra132/Tegra210 platforms
  Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler
  Tegra: remove weakly defined per-platform SiP handler
  Tegra: remove weakly defined PSCI platform handlers
  Tegra: remove weakly defined platform setup handlers
  Tegra: per-SoC DRAM base values
2020-02-05 10:11:44 +00:00
Mark Dykes 235c8174ff Merge "Coverity: remove unnecessary header file includes" into integration 2020-02-04 17:15:57 +00:00
Sandrine Bailleux 9eac8e958e Merge changes from topic "mp/separate_nobits" into integration
* changes:
  plat/arm: Add support for SEPARATE_NOBITS_REGION
  Changes necessary to support SEPARATE_NOBITS_REGION feature
2020-02-04 16:37:09 +00:00
Zelalem e6937287e4 Coverity: remove unnecessary header file includes
This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
2020-02-04 10:23:51 -06:00
Soby Mathew 44e3424e34 Merge "coverity: debugfs devfip remove comparisons to LONG_MAX" into integration 2020-02-04 15:03:59 +00:00
Manish Pandey d57a582a5b Merge "intel: agilex: Enable uboot BL31 loading" into integration 2020-02-04 13:42:36 +00:00
Olivier Deprez 47939f6725 coverity: debugfs devfip remove comparisons to LONG_MAX
CID 353228:  Integer handling issues  (CONSTANT_EXPRESSION_RESULT)

The checks on size and offset_address in get_entry always resolve to
false provided those fields are long long int and cannot be greater
than LONG_MAX.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0fac485a39ac4a40ae8c0d25a706ad74c795e130
2020-02-04 13:40:30 +00:00
Sandrine Bailleux 4ad18e5df3 Merge "BL2: Print ID of images we fail loading" into integration 2020-02-04 08:27:06 +00:00
Sandrine Bailleux a416325bc1 BL2: Print ID of images we fail loading
When Trusted Boot is enabled, images are loaded and authenticated
following up the root of trust. This means that between the initial
console message saying that an image is being loaded, and the final one
where it says that it failed to load it, BL2 may print several messages
about other images on the chain of trust being loaded, thus it is not
always clear which image we failed loading at the end of the day.

Change-Id: I3b189ec9d12c2a6203d16c8dbbb4fc117639c3c1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-02-03 16:11:56 +01:00
Imre Kis 8d52e16b45 doc: Remove backquotes from external hyperlinks
Since Sphinx 2.3.0 backquotes are replaced to \textasciigrave{} during
building latexpdf. Using this element in a \sphinxhref{} breaks the
build. In order to avoid this error backquotes must not be used in
external hyperlinks.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ie3cf454427e3d5a7b7f9829b42be45aebda7f0dd
2020-02-03 15:19:43 +01:00
Manish Pandey 5f62213e68 Merge "FDT wrappers: add functions for read/write bytes" into integration 2020-02-03 13:45:47 +00:00
Alexei Fedorov 0a2ab6e635 FDT wrappers: add functions for read/write bytes
This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes'
functions for read/write array of bytes from/to a given property.
It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i
files for builds with USE_ROMLIB=1 option.

Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-02-03 11:41:27 +00:00
Sandrine Bailleux 9db293d1f1 Merge "doc: qemu: fix and update documentation" into integration 2020-02-03 09:20:29 +00:00
Masahiro Yamada 62038be731 doc: qemu: fix and update documentation
The current URL for QEMU_EFI.fd is not found. Update the link to
point to the new one.

If you run the shell command as instructed, you will see this error:
  qemu-system-aarch64: keep_bootcon: Could not open 'keep_bootcon': No such file or directory

The part "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2" is the
kernel parameter, so it must be quoted.

As of writing, QEMU v4.2.0 is the latest, but it does not work for
TF-A (It has been fixed in the mainline.) QEMU v4.1.0 works fine.

With those issues addressed, I succeeded in booting the latest kernel.

Tested with QEMU v4.1.0 and Linux 5.5 (defconfig with no modification).
Update the tested versions.

Change-Id: Ic85db0e688d67b1803ff890047d37de3f3db2daa
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-03 18:10:45 +09:00
Pritesh Raithatha 029b45d1d4 Tegra186: memctrl: lock stream id security config
Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
2020-01-31 13:21:56 -08:00
Varun Wadekar 8ad1e475df Tegra194: remove support for simulated system suspend
This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.

Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:21:46 -08:00
Varun Wadekar 4a232d5b40 Tegra194: mce: fix multiple MISRA issues
This patch fixes violations of the following MISRA rules

* Rule 8.5  "An external object or function shall be declared once in
             one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
             object with a narrower essential type or of a different
             esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:21:35 -08:00
Varun Wadekar 64aa08fb16 Tegra: bpmp: fix multiple MISRA issues
This patch fixes violations for the following MISRA rules

* Rule 5.7  "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
             with a narrower essential type or of a different essential type
             category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
             conversions are performed shall have the same essential type
             category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
             shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
             or reserved macro name"

Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:21:24 -08:00
Varun Wadekar 8d4107f083 Tegra194: se: fix multiple MISRA issues
This patch fixes violations for the following MISRA rules

* Rule 8.4  "A compatible declaration shall be visible when an object or
             function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
             conversions are perdormed shall have the same essential type
             category"
* Rule 17.7 "The value returned by a function having non-void return
             type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:21:12 -08:00
Varun Wadekar 57c539f929 Tegra: compile PMC driver for Tegra132/Tegra210 platforms
The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:20:57 -08:00
Varun Wadekar f561a17967 Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler
This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:20:00 -08:00
Varun Wadekar ba37943d2d Tegra: remove weakly defined per-platform SiP handler
This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.

Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:19:48 -08:00
Varun Wadekar e44f86ef2b Tegra: remove weakly defined PSCI platform handlers
This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:19:38 -08:00
Varun Wadekar 39171cd033 Tegra: remove weakly defined platform setup handlers
This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:19:27 -08:00
Varun Wadekar 5f1803f90f Tegra: per-SoC DRAM base values
Tegra194 supports upto 64GB of DRAM, whereas the previous SoCs support
upto 32GB DRAM. This patch moves the common DRAM base/end macros to
individual Tegra SoC headers to fix this anomaly.

Change-Id: I1a9f386b67c2311baab289e726d95cef6954071b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-31 13:19:08 -08:00
Sandrine Bailleux 989429e872 Merge "Add support for documentation build as a target in Makefile" into integration 2020-01-31 07:35:30 +00:00
Tejas Patel 932f8b477b xilinx: versal: Pass result count to pm_get_callbackdata()
pm_get_callbackdata() expect result count and not total bytes of
result. Correct it by passing result count to pm_get_callbackdata().

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I01ce0002f7a753e81ea9fe65edde8420a13ed51a
2020-01-30 11:31:52 -08:00
Tejas Patel 70d0d759ad plat: xilinx: zynqmp: Use ARRAY_SIZE wherever possible
To find result count use ARRAY_SIZE for better readability.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I97201de4d43024e59fa78bd61937c86d47724ab5
2020-01-30 11:31:16 -08:00
Alexei Fedorov f69a5828b7 Merge "Use correct type when reading SCR register" into integration 2020-01-30 16:55:55 +00:00
Sandrine Bailleux b7e0ed2c71 Merge "Ignore the ctags file" into integration 2020-01-30 14:47:07 +00:00
Sandrine Bailleux dcd03ce7bb Merge changes from topic "sb/select-cot" into integration
* changes:
  Introduce COT build option
  cert_create: Remove references to TBBR in common code
  cert_create: Introduce COT build option
  cert_create: Introduce TBBR CoT makefile
2020-01-30 13:58:10 +00:00
Soby Mathew b1d810bd21 Merge "qemu: Implement PSCI_CPU_OFF." into integration 2020-01-29 15:36:30 +00:00
Soby Mathew 458dde3c44 Merge "T589: Fix insufficient ordering guarantees in bakery lock" into integration 2020-01-29 15:35:23 +00:00
Sandrine Bailleux 3bff910dc1 Introduce COT build option
Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.

Right now, the only available CoT is TBBR.

Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:33 +01:00
Sandrine Bailleux 067f7e9c52 cert_create: Remove references to TBBR in common code
In preparation of supporting alternate chains of trust, reword comments
and error messages that explicitly mentioned TBBR.

Change-Id: I85a0b08e16d0cd82f3b767fcc092d1f20f45939f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:32 +01:00
Sandrine Bailleux 43743ea57d cert_create: Introduce COT build option
It allows to select the desired chain of trust. Right now, only the TBBR
CoT is available.

At this stage, this build option only affects the tool itself. It is not
plugged into the rest of the build system yet. To use it:

 > make -C tools/cert_create COT=tbbr

Change-Id: I4484418f76d3c7b330d8653c978499a181534dcd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:32 +01:00
Sandrine Bailleux 3b24b66edc cert_create: Introduce TBBR CoT makefile
Move all TBBR-specific stuff out of the tool's makefile into a
sub-makefile. This will make it easier to define and select an alternate
chain of trust in the future.

Change-Id: I92e366a1999b74cf51127d1771b64b807cd94b29
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29 14:00:14 +01:00
Madhukar Pappireddy 6de32378f6 Add support for documentation build as a target in Makefile
Command to build HTML-formatted pages from docs:
make doc

Change-Id: I4103c804b3564fe67d8fc5a3373679daabf3f2e9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-29 06:26:09 -06:00
Andrew Walbran 33e8c56973 qemu: Implement PSCI_CPU_OFF.
This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
2020-01-29 10:50:25 +00:00
Soby Mathew 8efec9e097 Merge changes I0fb7cf79,Ia8eb4710 into integration
* changes:
  qemu: Implement qemu_system_off via semihosting.
  qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
2020-01-29 09:51:21 +00:00
Soby Mathew c1f118f1a7 Merge "Enable -Wredundant-decls warning check" into integration 2020-01-29 09:50:05 +00:00
Hadi Asyrafi 2a1e086677 intel: agilex: Enable uboot BL31 loading
This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c
2020-01-29 12:49:50 +08:00