Commit Graph

5388 Commits

Author SHA1 Message Date
Remi Pommarel 327ad2990a meson/gxl: Configure and boot SCP
On Amlogic gxl (s905x) SOC, in order to use SCP, bl31 has to send bl30
and bl301 firmware along with their SHA256 hash over scpi.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
2019-04-02 16:33:59 +02:00
Remi Pommarel b99f9224ed meson/gxl: Add support for SHA256 DMA engine
In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility that could be used to offload SHA-256
computations. This adds basic support of this hardware SHA-256
engine.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
2019-04-02 16:33:59 +02:00
Antonio Nino Diaz 95d0d13ce2 meson/gxl: Initial port of Amlogic Meson S905x (GXL)
The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running
at 1.5Ghz. It also contains a Cortex-M3 used as SCP.

This port is a minimal implementation of BL31 capable of booting
mainline U-Boot and Linux:

- Partial SCPI support.
- Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF).
- GICv2 driver set up.
- Basic SIP services (read efuse data, enable/disable JTAG).

This port has been tested on a lepotato.

Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
2019-04-02 16:33:58 +02:00
Antonio Nino Diaz 5db5930baf SPM: Ignore empty regions in resource description
Instead of letting the code run until another error is reached, return
early.

Change-Id: I6277a8c65101d3e39b0540099c2a3063584a7dbd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-04-02 14:52:55 +01:00
Valentine Barshak b709fe9c43 rcar_gen3: plat: Add R-Car V3M support
Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---
Marek: Update on top of mainline ATF/master
2019-04-02 15:37:00 +02:00
Antonio Niño Díaz 0a4bf763f3
Merge pull request #1914 from marex/arm/master/d3draak-v2.0.1
Arm/master/d3draak v2.0.1
2019-04-02 14:16:27 +01:00
Marek Vasut 15652ec3ff rcar_gen3: drivers: qos: Add D3 QoS tables
Add QoS tables for R-Car D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut b645d22b50 rcar_gen3: drivers: pfc: Add D3 PFC tables
Add PFC tables for R-Car D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut b60b9b5a66 rcar_gen3: drivers: ddr_a: Add D3 DDR init
Add R-Car D3 DDR initialization code. The code is in staging and needs
cleanup, and possibly can even be merged with the E3 init code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut cdea546d70 rcar_gen3: drivers: swdt: Add D3 support
Add WTCNT register configuration for the D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut ada66133e9 rcar_gen3: drivers: scif: Add D3 support
Add SCIF configuration specifics for the D3 SoC, that is detection
of the D3 SoC and SCBRR configuration.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut 5c1d535730 rcar_gen3: drivers: pwrc: Add D3 support
The D3 SoC has one CPU core, just return 1 as a CPU number.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut 90ff8ba6be rcar_gen3: drivers: rom: Mark NEW table as D3 compatible
Add comment into the ROM driver that the new table is also D3 compatible.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut bfbf5df405 rcar_gen3: plat: Add initial D3 support
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code
will be added separately.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Marek Vasut 5b4f022be4 rcar_gen3: plat: Print DRAM bank size in MiB if below 1 GiB
Print the DRAM bank size in MiB instead of GiB in case the bank size
is smaller than 1 GiB. This prevents printing zeroes on systems with
small DRAM sizes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-04-02 03:40:51 +02:00
Antonio Niño Díaz 18ff0b61bb
Merge pull request #1886 from ambroise-arm/av/static-checks
Fix extra compilation warnings
2019-04-01 11:25:21 +01:00
Antonio Niño Díaz 9cadccdff3
Merge pull request #1913 from marex/arm/master/m3wulcb-v2.0.1
rcar_gen3: plat: Set M3W ULCB DRAM size to 2 GiB
2019-04-01 11:04:04 +01:00
Antonio Niño Díaz d037bec9bd
Merge pull request #1898 from hadi-asyrafi/watchdog
intel: Enable watchdog timer on Intel S10 platform
2019-04-01 11:03:50 +01:00
Ambroise Vincent 279faa6d5d BL1: Fix type consistency
Change function signatures and fix sign-compare warnings.

Change-Id: Iaf755d61e6c54c3dcf4f41aa3c27ea0f6e665fee
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-01 10:43:42 +01:00
Ambroise Vincent 7a79328c3a SPM: Create SPCI auxiliary function
Fix variable shadowing warnings and prevent code duplication.

Change-Id: Idb29cc95d6b6943bc012d7bd430afa0e4a7cbf8c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-01 10:43:42 +01:00
Ambroise Vincent bde2836fcc Remove several warnings reported with W=2
Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.

The libraries are compiling with warnings (which turn into errors with
the Werror flag).

Outside of libraries, some warnings cannot be fixed.

Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-01 10:43:42 +01:00
Ambroise Vincent 609e053caa Remove several warnings reported with W=1
Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.

The libraries are compiling with warnings (which turn into errors with
the Werror flag).

Outside of libraries, some warnings cannot be fixed without heavy
structural changes.

Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-01 10:43:42 +01:00
Soby Mathew ee80da114b
Merge pull request #1911 from lmayencourt/lm/update_gcc
doc: Suggest to use the latest version of GCC 8.2
2019-03-29 10:53:57 +00:00
Soby Mathew 683ac46e27
Merge pull request #1912 from pbeesley-arm/pb/spm-reword
doc: Clarify draft status of SPCI and SPRT specs
2019-03-29 10:53:25 +00:00
Paul Beesley bf32bc9c50 doc: Clarify draft status of SPCI and SPRT specs
These SPM-related specifications are mentioned in the readme and
the change log. Update references to these specs to make it clear
that they are in draft form and are expected to change.

Change-Id: Ia2791c48c371a828246d96f102a402747cd69f96
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-29 10:16:12 +00:00
Louis Mayencourt 0042f5784b doc: Suggest to use the latest version of GCC 8.2
The latest version of GCC are required to use the new features of TF-A.
Suggest to use the latest version available on developer.arm.com instead
of the version specified on the Linaro Release notes.
At the time of writing, GCC 8.2-2019.01 is the latest version available.

Change-Id: Idd5c00749e39ca9dc8b7c5623b5d64356c9ce6e5
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-03-29 10:02:21 +00:00
Soby Mathew 2f13be3637
Merge pull request #1908 from soby-mathew/sm/update_ver
Update TF-A version to 2.1
2019-03-28 14:34:36 +00:00
Soby Mathew 5debac490d
Merge pull request #1910 from soby-mathew/sm/mb_ver_doc
docs: List MB version dependancy for Juno FWU as known issue
2019-03-28 14:30:40 +00:00
Soby Mathew 97fc1968ae docs: List MB version dependency for Juno FWU as known issue
Change-Id: Ib37215ca4c9b515e54054290952eed5034582ba4
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-03-28 14:25:09 +00:00
Soby Mathew 8f7b793e18
Merge pull request #1909 from ambroise-arm/av/doc-update
Documentation: update tested platforms
2019-03-28 13:50:17 +00:00
Ambroise Vincent 6192448a43 Documentation: update tested platforms
Update both the readme and user guide on their shared "platform"
section.

Change-Id: Ia1f30acda45ac8facdcb7d540800191cdf6cdacf
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-28 12:51:48 +00:00
Soby Mathew cc429178ce
Merge pull request #1906 from pbeesley-arm/pb/readme
doc: Prepare readme for 2.1 release
2019-03-27 12:08:16 +00:00
Soby Mathew 512650c348
Merge pull request #1907 from pbeesley-arm/pb/changelog
doc: Update change log for v2.1
2019-03-27 12:03:25 +00:00
Soby Mathew 2a3178b74d
Merge pull request #1905 from ambroise-arm/av/2.1-docs
Update user guide for 2.1 release
2019-03-27 11:07:20 +00:00
Paul Beesley 9e437f2964 doc: Update change log for v2.1
Change-Id: Ib6a20ffdddad11b9629d7dca7f841182299bf860
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-27 10:53:45 +00:00
Paul Beesley ca7145c5ca doc: Update readme.rst for v2.1 release
Change-Id: Id3ae11a401a2e5290bb1980f1f349fc3cf49c7d6
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-27 10:43:20 +00:00
Marek Vasut 5a21f31331 rcar_gen3: plat: Set M3W ULCB DRAM size to 2 GiB
The M3W ULCB board has 2 GiB of DRAM, set it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-03-27 00:16:30 +01:00
Soby Mathew 6f8261b0a7 Update TF-A version to 2.1
Change-Id: I6d8a6419df4d4924214115facbce90715a1a0371
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-03-26 15:51:59 +00:00
Ambroise Vincent 68126051d3 docs: Update user guide
Make sure the steps in the user guide are up to date and can be
performed out of the box.

Change-Id: Ib4d959aa771cf515f74e150aaee2fbad24c18c38
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-26 14:59:34 +00:00
Paul Beesley 9dc5f21ec2 doc: Add contents.rst to link to pages
This is the temporary contents page that links
to all other documents (except platform ports).

This page is needed during the
trustedfirmware.org migration, before we have a
Sphinx rendering pipeline set up, because cgit
doesn't offer a good way to view rendered docs
while browsing the tree. We need to have a links
page that can be opened from the cgit 'about'
view.

Change-Id: I3ad87a9fa8a14dc8e371aac7ee473575fed316bf
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-03-26 14:49:17 +00:00
Soby Mathew 2c269b4736
Merge pull request #1904 from lmayencourt/lm/move_pie_fixup
PIE: Fix reloc at the beginning of bl31 entrypoint
2019-03-25 11:00:46 +00:00
Louis Mayencourt 330ead8065 PIE: Fix reloc at the beginning of bl31 entrypoint
The relocation fixup code must be called at the beginning of bl31
entrypoint to ensure that CPU specific reset handlers are fixed up for
relocations.

Change-Id: Icb04eacb2d4c26c26b08b768d871d2c82777babb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-03-25 10:54:59 +00:00
Dimitris Papastamos 981db33f77
Merge pull request #1903 from thloh85-intel/thloh85-integration
driver: synosys: Fix SD MMC not initializing correctly
2019-03-22 16:26:28 +00:00
Tien Hock, Loh 2baa727011 driver: synosys: Fix SD MMC not initializing correctly
dw_params.mmc_dev_type should be assigned before mmc_init, otherwise SDMMC
initialization will fail as the initialization treats the device as EMMC
instead of SD.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
2019-03-22 12:54:31 +08:00
Dimitris Papastamos 46d58f80af
Merge pull request #1902 from jts-arm/romlib
ROMLIB bug fixes
2019-03-21 12:40:35 +00:00
John Tsichritzis ae2e01b876 ROMLIB bug fixes
Fixed the below bugs:
1) Bug related to build flag V=1: if the flag was V=0, building with
ROMLIB would fail.
2) Due to a syntax bug in genwrappers.sh, index file entries marked as
"patch" or "reserved" were ignored.
3) Added a prepending hash to constants that genwrappers is generating.
4) Due to broken dependencies, currently the inclusion functionality is
intentionally not utilised. This is why the contents of romlib/jmptbl.i
have been copied to platform specific jmptbl.i files. As a result of the
broken dependencies, when changing the index files, e.g. patching
functions, a clean build is always required. This is a known issue that
will be fixed in the future.

Change-Id: I9d92aa9724e86d8f90fcd3e9f66a27aa3cab7aaa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-03-21 10:51:07 +00:00
Muhammad Hadi Asyrafi Abdul Halim 10e70f87e0 intel: Enable watchdog timer on Intel S10 platform
Watchdog driver support & enablement during platform setup

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
2019-03-21 10:35:24 +08:00
Dimitris Papastamos cc0dcf428f
Merge pull request #1899 from jts-arm/docs
Add USE_ROMLIB build option to user guide
2019-03-20 12:36:17 +00:00
Dimitris Papastamos 3481800fbd
Merge pull request #1887 from ambroise-arm/av/a76-cve
Cortex-A76: Optimize CVE_2018_3639 workaround
2019-03-20 11:18:20 +00:00
Dimitris Papastamos 5e5c77dbe4
Merge pull request #1901 from AlexeiFedorov/af/restore_pauth_context_smc
Restore PAuth context in case of unknown SMC call
2019-03-20 11:17:33 +00:00