Commit Graph

3683 Commits

Author SHA1 Message Date
Yann Gautier 5fbcdd056b tools: Add stm32image tool into TF-A
This tools adds a specific header to ST TF-A binary.
This header is used by STM32MP1 ROM code to check the bootloader.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:18:37 +02:00
Yann Gautier 587f60fac5 stm32mp1: Add device tree files
Those device tree files are taken from STM32MP1 U-Boot and Linux.
And they are updated to fit TF-A needs.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:18:35 +02:00
Yann Gautier 964dfee1a2 stm32mp1: Add BL32 SP_min secure monitor
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2018-07-24 17:18:32 +02:00
Yann Gautier 10a511ceaa stm32mp1: Add DDR support and its security with TZC400
The DDR driver is under dual license, BSD and GPLv2.
The configuration parameters are taken from device tree.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:18:19 +02:00
Yann Gautier e4f559ff54 stm32mp1: Add PMIC support
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2018-07-24 17:15:13 +02:00
Yann Gautier 278c34df06 stm32mp1: Add console support
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:14:39 +02:00
Yann Gautier e58a53fb72 stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:14:22 +02:00
Yann Gautier 6a339a4952 stm32mp1: Add GPIO support
The management of pinctrl nodes of device tree is also added.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2018-07-24 17:14:08 +02:00
Yann Gautier 7839a05090 stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
2018-07-24 17:13:36 +02:00
Yann Gautier 4353bb20cc Introduce STMicroelectronics STM32MP1 platform
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.

STM32MP1 uses BL2 compiled with BL2_AT_EL3.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2018-07-24 17:11:43 +02:00
Yann Gautier 836be059bb Add STMicroelectronics to the list of contributors
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-07-24 17:10:13 +02:00
danh-arm cffb003428
Merge pull request #1488 from b49020/integration
synquacer: Enable optional OP-TEE support
2018-07-24 14:37:23 +01:00
danh-arm 790e6c5b96
Merge pull request #1485 from jeenu-arm/ras
Double-fault and fatal error handling support
2018-07-24 14:36:43 +01:00
Sumit Garg 6cb2a39703 synquacer: Enable optional OP-TEE support
OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
2018-07-24 17:12:22 +05:30
danh-arm df0b5a4b71
Merge pull request #1487 from hzhuang1/tbb_bl1
hikey: include TBB in BL1
2018-07-24 11:06:24 +01:00
Haojian Zhuang 99eb5ae86d hikey: include TBB in BL1
BL1 is used in recovery mode on HiKey. The TBB implementation
on HiKey is in BL2. It means that user need to build ATF BL2
with TBB and ATF BL1 with non-TBB. It's inconvenient.

So include TBB in BL1, too.

Signed-off-by: Teddy Reed <teddy@prosauce.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-07-22 09:35:44 +08:00
danh-arm ba0248b52d
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
Marvell support for Armada 8K SoC family
2018-07-19 17:11:32 +01:00
danh-arm 992a353613
Merge pull request #1483 from antonio-nino-diaz-arm/an/rpi3-psci
rpi3: PSCI and Linux boot improvements
2018-07-19 15:37:54 +01:00
danh-arm 224e1abad8
Merge pull request #1481 from antonio-nino-diaz-arm/an/xlat-refactor
xlat: More refactoring
2018-07-19 15:33:19 +01:00
danh-arm e4686fd860
Merge pull request #1449 from theopolis/hikey-tbb
hikey: Add experimental TBB support
2018-07-19 11:49:56 +01:00
danh-arm 8ff0dfa79c
Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr
Misc arch.h fixes and cleanup
2018-07-19 11:36:58 +01:00
Jeenu Viswambharan 4431aae973 RAS: Update porting guide with RAS platform handlers
Change-Id: I76cb1d387ab51ee48fa91fd7458c7041b454ceee
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:18 +01:00
Jeenu Viswambharan eaeaa4d048 RAS: Introduce handler for EL3 EAs
External Aborts while executing in EL3 is fatal in nature. This patch
allows for the platform to define a handler for External Aborts received
while executing in EL3. A default implementation is added which falls
back to platform unhandled exception.

Change-Id: I466f2c8113a33870f2c7d2d8f2bf20437d9fd354
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:18 +01:00
Jeenu Viswambharan d5a23af50f RAS: Introduce handler for Double Faults
Double fault is when the PE receives another error whilst one is being
handled. To detect double fault condition, a per-CPU flag is introduced
to track the status of error handling. The flag is checked/modified
while temporarily masking external aborts on the PE.

This patch routes double faults to a separate platform-defined handler.

Change-Id: I70e9b7ba4c817273c55a0af978d9755ff32cc702
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:18 +01:00
Jeenu Viswambharan b56dc2a98c RAS: Introduce handler for Uncontainable errors
Uncontainable errors are the most severe form of errors, which typically
mean that the system state can't be trusted any more. This further means
that normal error recovery process can't be followed, and an orderly
shutdown of the system is often desirable.

This patch allows for the platform to define a handler for Uncontainable
errors received. Due to the nature of Uncontainable error, the handler
is expected to initiate an orderly shutdown of the system, and therefore
is not expected to return. A default implementation is added which falls
back to platform unhandled exception.

Also fix ras_arch.h header guards.

Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-19 10:13:17 +01:00
Konstantin Porotchkin 23e0fe52de make: support libraries in MAKE_BL macro
Add support for BLx stages to use libraries in MAKE_BL macro.
This change does not affect BL stages that do not have
BL_LIBS variable defined in their makefiles.
However in case that BL wants to use external library
(for instance vendor-specific DDR initialization code supplied
as a library), this patch will allow to build BL image linked
with such library.

Change-Id: Ife29069a72dc4aff833db6ef8b828736d6689b78
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 255f5c8f88 io: Allow image load to address zero
Remove assert on buffer address equal zero.
Marvell uses address 0x0 for loading BL33,
so this check is irrelevant and breaks the
debug builds on Marvell platforms.

Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/54589
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 34ec7ec310 plat: marvell: Add board support for A8K platform
Add support for A8K platform boards

Change-Id: Ife025d930d2ab6cabbc13bbe19b2273cc1c938c8
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 486f868bab plat: marvell: Add common ARMADA platform components
Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.

Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 939e085654 docs: Add Marvell build and porting documents
Change-Id: I341440701b7e5e3555e604dd9d0a356795e6c4fb
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 434e029ddd tools: add support for Marvell doimage
Add Marvell "doimage" utility support.
The "doimage" utility allows to create flash images compatible
with Marvell BootROM image format. Additionally this tool
allows the flash image parsing and verification.

Change-Id: Ie8d7ccd0cc2978684e7eecb695f375395fc749ee
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin f87e94491f marvell: drivers: Add i2c driver
Add i2c driver for A8K SoC family.

Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 0ade8cd892 mvebu: cp110: add COMPHY driver
Add COMPHY driver for usage in a runtime service.

Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin d5a6f86cdf marvell: drivers: Add thermal driver
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration

Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 152b0e4717 marvell: drivers: Add L3/system cache management drivers
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810

Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin bc6206f7f6 lib: cpu: Add L2 cache aux control register definition to CA72
Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 031542fc24 marvell: drivers: Add MoChi drivers
Add ModularChip and MCI drivers for A8K SoC family.
ModularChip drivers include support for the internal building
blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110

Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin c0474d5843 marvell: drivers: Add address decoding units drivers
Add address decoding unit drivers for Marvell SoCs.

Address decoding flow and address translation units chart
are located at docs/marvell/misc/mvebu-a8k-addr-map.txt

Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Konstantin Porotchkin 752faf8fce maintainers: Add Marvell to maintainers list
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2018-07-18 18:48:30 +03:00
Soby Mathew 2e4eea1b11
Merge pull request #1471 from Anson-Huang/master
Add i.MX8QX/i.MX8QM power management feature
2018-07-18 13:35:29 +01:00
Sandrine Bailleux e62ea09bfe Fix HCPTR.TCP11 bit definition
Change-Id: I98f23f6cebcf984b57efc5449b75ff702e1984a0
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-07-18 12:19:41 +02:00
Antonio Nino Diaz 30399885f5 Fix types of arch.h definitions
Define the values as unsigned int or unsigned long long based on the
actual size of the register. This prevents subtle issues caused by
having a type that is too small. For example:

    #define OPTION_ENABLE 0x3
    #define OPTION_SHIFT  32

    uint64_t mask = OPTION_ENABLE << OPTION_SHIFT;

Because OPTION_ENABLE fits in an int, the value is considered an int.
This means that, after shifting it 32 places to the left, the final
result is 0. The correct way to define the values is:

    #define OPTION_ENABLE ULL(0x3)
    #define OPTION_SHIFT  U(32)

In this case, the compiler is forced to use a 64 bit value from the
start, so shifting it 32 places to the left results in the expected
value.

Change-Id: Ieaf2ffc2d8caa48c622db011f2aef549e713e019
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-18 11:09:54 +01:00
Antonio Nino Diaz 0107aa49b4 Add missing parentheses to macros in arch.h
Change-Id: Ifea46da46d1bfd01b341acfad75df5bcab48a204
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-18 11:09:14 +01:00
Soby Mathew 344e40379c
Merge pull request #1480 from sandrine-bailleux-arm/topics/sb/debug-macros
Always compile debug macros
2018-07-18 10:48:03 +01:00
Jeenu Viswambharan ee6ff1bb37 RAS: Validate stack pointer after error handling
RAS handling flows might involve using setjmp/longjump calls introduced
in earlier patches; therefore, it'd be good to make sure the stack has
been unwound completely after the handling.

This patch inserts ASM assertions on the RAS handling path to validate
stack.

Change-Id: I59d40d3122010c977cdeab3cce3160f3909e7e69
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-17 08:31:31 +01:00
Jeenu Viswambharan df8f3188d7 RAS: Move EA handling to a separate file
A new file ea_delegate.S is introduced, and all EA-related functions are
moved into it. This makes runtime_exceptions.S less crowded and reads
better.

No functional changes.

Change-Id: I64b653b3931984cffd420563f8e8d1ba263f329f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-07-17 08:31:31 +01:00
Antonio Nino Diaz aa49bde8a3 rpi3: Move NS-DRAM out of the protected region
The Non-secure DRAM region shouldn't be protected in the range specified
in the Linux command line with memmap.

This change also increases the size of the Secure DRAM region.

Change-Id: I306e9e443a84b834c99739f54a534a3ca3be2424
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 97fb05e1ec rpi3: Switch addresses of kernel and DTB
In the memory map of the documentation the kernel only had 16MiB of
allocated space. This leaves very little room for growth, so the
addresses of the DTB and the kernel have been interchanged.

The documentation has been updated to reflect this change.

Change-Id: Ib6eab69f047fa88561fb755397ce3a0b356c8860
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 5e2e024b3d rpi3: Update documentation
Add information about direct Linux kernel boot for kernels that support
PSCI.

Change-Id: I05f76aa36398edabf411cb25a646437af1862e6e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00
Antonio Nino Diaz 76c944a48d rpi3: Add support for direct Linux kernel boot
This option allows the Trusted Firmware to pass the correct arguments to
a 32 or 64-bit Linux kernel without the need of an intermediate loader
such as U-Boot.

Change-Id: I2b22e8933fad6a614588ace559f893e97329801f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-07-16 15:56:42 +01:00