Commit Graph

9908 Commits

Author SHA1 Message Date
Jona Stubbe 9565962c37 refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication
Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.

Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de>
Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2022-01-04 15:26:43 +01:00
André Przywara e752fa4a4c Merge "feat(allwinner): allow to skip PMIC regulator setup" into integration 2022-01-01 02:16:14 +01:00
Madhukar Pappireddy f72827b842 Merge "fix(mt8186): remove unused files in drivers/mcdi" into integration 2021-12-30 16:38:40 +01:00
Rex-BC Chen bc714bafe7 fix(mt8186): remove unused files in drivers/mcdi
We don't use mbox drivers which are implemented in these files for
mcdi, so remove related files from mcdi folder.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Idea5ebe5b25f91066ebd653cdcdafe65ca292b0f
2021-12-30 17:21:33 +08:00
Andre Przywara 67412e4d7a feat(allwinner): allow to skip PMIC regulator setup
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.

To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.

After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
2021-12-27 15:32:22 +00:00
Joanna Farley a006606f3c Merge "feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX" into integration 2021-12-24 11:26:32 +01:00
Madhukar Pappireddy 93b153b5bf Merge changes from topic "st_regulator" into integration
* changes:
  feat(st-sdmmc2): manage cards power cycle
  feat(stm32mp1): register fixed regulator
  feat(st-drivers): introduce fixed regulator driver
  refactor(st): update CPU and VDD voltage get
  refactor(stm32mp1-fdts): update regulator description
  refactor(st-pmic): use regulator framework for DDR init
  feat(st-pmic): register the PMIC to regulator framework
  refactor(st-pmic): split initialize_pmic()
  feat(stm32mp1): add regulator framework compilation
  feat(regulator): add a regulator framework
  feat(stpmic1): add new services
  feat(stpmic1): add USB OTG regulators
  refactor(st-pmic): improve driver usage
  refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
  refactor(stm32mp1): re-order drivers init
2021-12-24 00:13:50 +01:00
Madhukar Pappireddy 91a8bd660a Merge "fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32" into integration 2021-12-22 23:57:16 +01:00
Madhukar Pappireddy dd14d0f63f Merge "fix(fiptool): respect OPENSSL_DIR" into integration 2021-12-22 22:24:44 +01:00
Bipin Ravi 9697e4596c Merge "fix(trp): Distinguish between cold and warm boot" into integration 2021-12-22 21:13:03 +01:00
Madhukar Pappireddy b3c4101541 Merge changes from topic "uart1_console" into integration
* changes:
  feat(versal): add UART1 as console
  feat(zynqmp): add uart1 as console
2021-12-22 19:18:15 +01:00
Madhukar Pappireddy 0ca4b4b79e Merge changes from topic "clock_framework" into integration
* changes:
  feat(st): use newly introduced clock framework
  feat(clk): add a minimal clock framework
2021-12-22 19:17:57 +01:00
Madhukar Pappireddy ed780b0b40 Merge changes I41001484,Ic734696a,I84741535,I85aaaf3a,Ibd5423b7, ... into integration
* changes:
  feat(plat/mediatek/mt8186): add reboot function for PSCI
  feat(plat/mdeiatek/mt8186): add power-off function for PSCI
  feat(plat/mediatek/mt8186): apply erratas for MT8186
  feat(plat/mediatek/mt8186): add MCDI drivers
  feat(plat/mediatek/mt8186): add CPU hotplug
  feat(plat/mediatek/mt8186): add RTC drivers
  fix(plat/mediatek/mt8186): extend MMU region size
  feat(plat/mediatek/mt8186): add DCM driver
  feat(plat/mediatek/mt8186): add pinctrl support
  feat(plat/mediatek/mt8186): add sys_cirq support
  feat(plat/mediatek/mt8186): initialize GIC
  feat(plat/mediatek/mt8186): add SiP service
  feat(plat/mediatek/mt8186): add pwrap and pmic driver
  feat(plat/mediatek/mt8186): initialize delay_timer
  feat(plat/mediatek/mt8186): initialize systimer
  feat(plat/mediatek/mt8186): add EMI MPU basic driver
2021-12-22 19:16:55 +01:00
Madhukar Pappireddy d76346b940 Merge "fix(fiptool): avoid packing the zero size images in the FIP" into integration 2021-12-22 15:32:14 +01:00
Madhukar Pappireddy b48121b6fd Merge "fix(errata): workaround for Cortex X2 erratum 2058056" into integration 2021-12-22 15:23:00 +01:00
Yann Gautier 258bef913a feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required.
For this we need to:
- disable vmmc-supply regulator
- make the power cycle required for SDMMC2 peripheral
- enable regulators

Change-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet 967a8e63c3 feat(stm32mp1): register fixed regulator
Register fixed regulator in BL2.

Change-Id: I24292f549b2cd24fb717fbb68eb95af7aa68e3b9
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet 5d6a2646f7 feat(st-drivers): introduce fixed regulator driver
Fixed regulator is mainly used when no pmic is available

Change-Id: Ib6a998684bcb055ba95a093bee563372d9051474
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier c39c658e75 refactor(st): update CPU and VDD voltage get
Use regulator framework to get CPU and VDD power supplies.

Change-Id: Ice745fb21ff10e71ef811e747165499c2e19253e
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet 67d95409ba refactor(stm32mp1-fdts): update regulator description
Update regulator description to match with pmic driver updates.
vref_ddr does not support over-current protection.
vtt_ddr is set to sink source mode.

Change-Id: I725f35b091ca8c230994c2b5f81693ebc97bf4aa
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet 0ba71ac901 refactor(st-pmic): use regulator framework for DDR init
Use regulator framework for DDR initialization.

Change-Id: I9dffe499ca12cdc35904de7daf2dda821b267a31
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 85fb175b5e feat(st-pmic): register the PMIC to regulator framework
Register the PMIC to the regulator framework.

Change-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon ae7792e058 refactor(st-pmic): split initialize_pmic()
print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after initialize_pmic() in BL2.

Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier bba9fdee58 feat(stm32mp1): add regulator framework compilation
Add required macro PLAT_NB_RDEVS in platform code, and update
platform.mk to compile regulator framework.

Change-Id: I9dc7a0a4c4f5a23d9bedda368d407612c9cd21cd
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet d5b4a2c4e7 feat(regulator): add a regulator framework
Add a regulator framework to:
- provide an interface to consumers and drivers,
- connect consumers with drivers,
- handle most of devicetree-parsing,
- handle always-on and boot-on regulators,
- handle min/max voltages,

Change-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22 14:04:32 +01:00
Pascal Paillet ea552bf5a5 feat(stpmic1): add new services
Add support for ICC, sink mode, bypass mode,
active discharge and list voltages.
Handle LDO3 sink source mode in a different way to avoid
setting voltage while in sink source mode.

Change-Id: Ib1b909fd8a153f542917f650e43e24317a570534
Signed-off-by: Pascal Paillet <p.paillet@st.com>
2021-12-22 14:04:32 +01:00
Etienne Carriere 13fbfe046e feat(stpmic1): add USB OTG regulators
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated during the suspend/resume power sequence
as per FDT description for stm32mp15x-xxx boards from
STMicroelectronics.

Change-Id: I6217de707e49882bd5a9100db43e0d354908800d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon c77c7d9e30 refactor(st-pmic): improve driver usage
Store status of dt_pmic_status() as local static variable,
this avoids parsing DT several times.
In the same way, store nodes in dt_pmic_i2c_config() and
in dt_get_pmic_node() as local static variables.

Change-Id: I4585e9dfdde2847a369bffcc6f2b39ecc2b74de1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Nicolas Le Bayon 16e56a75de refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean
Improve use and readability.

Change-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 0c16e7d2fb refactor(stm32mp1): re-order drivers init
SYSCFG can be initialized later, after console is up, to display the
warnings or messages it could issue.
PMIC should be initialized earlier, before SYSCFG init.

Change-Id: Icc3a1366083a1b1fde7f0e173645449b4c04c49b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-22 14:04:32 +01:00
Yann Gautier 24ab2c0af7 fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32
With patch [1], ENABLE_SVE_FOR_NS is always enable.
Disable it for AARCH32 platforms, as the feature is not supported.
The warning message is replaced with an error, and the second override
is removed.

[1] dc78e62d80 ("feat(sme): enable SME functionality")

Change-Id: Ic9c5e2612c9e00bd0d37ca3b59537e39270c9799
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-22 14:03:19 +01:00
Yann Gautier 33667d299b feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2021-12-22 13:08:09 +01:00
Gabriel Fernandez 847c6bc8e6 feat(clk): add a minimal clock framework
This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compiled for STM32MP1.

Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
2021-12-22 13:07:23 +01:00
Venkatesh Yadav Abbarapu 2c791499c2 feat(versal): add UART1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ifcd3c331cf6ce4afb0074357c92fc4addb9438b6
2021-12-22 03:56:42 -07:00
Venkatesh Yadav Abbarapu ea66e4af0b feat(zynqmp): add uart1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I08f69b65b78b967ceb7159f4a467aa5982b1f791
2021-12-22 03:56:16 -07:00
Rex-BC Chen 24dd5a7b71 feat(plat/mediatek/mt8186): add reboot function for PSCI
Add system_reset function in PSCI operations.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I41001484f6244bd6ae7dedcfb6ce71cd6c035a1e
2021-12-22 18:06:53 +08:00
Rex-BC Chen a68346a772 feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab1b71ae85bca6ed08e544a522ce5c95
2021-12-22 18:06:53 +08:00
Rex-BC Chen 572f8adbb0 feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84741535fbe429f664092f624c2da653532204cd
2021-12-22 18:06:53 +08:00
Garmin.Chang 06cb65ef07 feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.

TEST=build pass
BUG=b:202871018

Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
2021-12-22 18:06:53 +08:00
Garmin.Chang 1da57e54b2 feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.

TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018

Change-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
2021-12-22 18:06:53 +08:00
Yuchen Huang 6e5d76bac8 feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.

TEST=build pass
BUG=b:202871018

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ib48c07204c4a614072ba710c042794b59e8a902a
2021-12-22 18:06:53 +08:00
Rex-BC Chen 0fe7ae9c64 fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.

This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I520c51338578bd68756cd02603ce6783f93daf51
2021-12-22 18:06:53 +08:00
Edward-JW Yang 95ea87ffc2 feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.

1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.

TEST=build pass
BUG=b:202871018

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
2021-12-22 18:06:53 +08:00
Guodong Liu af5a0c40af feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.

TEST=build pass
BUG=b:202871018

Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f
2021-12-22 18:06:53 +08:00
Zhengnan Chen 109b91e38c feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.

TEST=build pass
BUG=b:202871018

Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787
2021-12-22 18:06:53 +08:00
Christine Zhu 206f125cc1 feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.

TEST=build pass
BUG=b:202871018

Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d029983c7ce48fa116fafa7fa78c65349308014
2021-12-22 18:06:53 +08:00
Rex-BC Chen 5aab27dc42 feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde21197754f6367
2021-12-22 18:06:53 +08:00
James Lo 5bc88ec61c feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.

TEST=build pass
BUG=b:202871018

Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2
2021-12-22 18:06:53 +08:00
Rex-BC Chen d73e15e66a feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f52d1c674537795cc478015c83cca0f872df60
2021-12-22 18:06:53 +08:00
Rex-BC Chen a6a0af57c3 feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d094410d178e4203e3a9294b851a30ba150
2021-12-22 18:06:53 +08:00