Commit Graph

1129 Commits

Author SHA1 Message Date
Joanna Farley e5bc3ef3b5 Merge "feat(gic600ae): introduce support for Fault Management Unit" into integration 2021-09-06 21:00:56 +02:00
Varun Wadekar 2c248ade2e feat(gic600ae): introduce support for Fault Management Unit
The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:

* Provides software the means to enable or disable a Safety Mechanism
  within a GIC block.
* Receives error signaling from all Safety Mechanisms within other GIC
  blocks.
* Maintains error records for each GIC block, for software inspection
  and provides information on the source of the error.
* Retains error records across functional reset.
* Enables software error recovery testing by providing error injection
  capabilities in a Safety Mechanism.

This patch introduces support to enable error detection for all safety
mechanisms provided by the FMU. Platforms are expected to invoke the
initialization function during cold boot.

The support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU
makefile variable. The default value of this variable is '0'.

Change-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2021-09-01 08:24:33 -07:00
Jiafei Pan 08695df91d refactor(plat/nxp): refine api to read SVR register
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
2021-08-26 10:08:57 +08:00
Joanna Farley c87f2c1dd3 Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes:
  feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
  feat(plat/rcar3): add a DRAM size setting for M3N
  feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
  feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
  feat(drivers/rcar3): ddr: add function to judge a DDR rank
  fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
  fix(drivers/rcar3): i2c_dvfs: fix I2C operation
  fix(drivers/rcar3): fix CPG registers redefinition
  fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
  fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
  refactor(plat/rcar3): factor out DT memory node generation
  feat(plat/rcar3): add optional support for gzip-compressed BL33
2021-08-13 10:16:20 +02:00
Manish Pandey e528bc22eb Merge changes from topic "st_fip_fconf" into integration
* changes:
  feat(io_mtd): offset management for FIP usage
  feat(nand): count bad blocks before a given offset
  feat(plat/st): add helper to save boot interface
  fix(plat/st): improve DDR get size function
  refactor(plat/st): map DDR secure at boot
  refactor(plat/st): rework TZC400 configuration
2021-08-13 00:22:55 +02:00
Pankaj Gupta 050a99a62f refactor: moved drivers hdr files to include/drivers/nxp
NXP drivers header files are moved:
  - from:  drivers/nxp/<xx>/*.h
  - to  :  include/drivers/nxp/<xx>/*.h

To accommodate these changes each drivers makefiles
drivers/nxp/<xx>/xx.mk, are updated.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
2021-08-03 12:19:56 +02:00
Manish V Badarkhe c885d5c84d refactor(hw_crc32): renamed hw_crc32 to tf_crc32
Renamed hw_crc32 to tf_crc32 to make the file and function
name more generic so that the same name can be used in upcoming
software CRC32 implementation.

Change-Id: Idff8f70c50ca700a4328a27b49d5e1f14d2095eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02 17:15:41 +01:00
Manish V Badarkhe c0bfc88f8e feat(fwu): avoid NV counter upgrade in trial run state
Avoided NV counter update when the system is running in
trial run state.

Change-Id: I5da6a6760f8a9faff777f2ff879156e9c3c76726
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02 17:15:40 +01:00
Manish V Badarkhe 0ec3ac60d8 feat(fwu): add FWU driver
Implemented FWU metadata load and verification APIs.
Also, exported below APIs to the platform:
1. fwu_init - Load FWU metadata in a structure. Also, set the
	      addresses of updated components in I/O policy
2. fwu_is_trial_run_state - To detect trial run or regular run
			    state

Change-Id: I67eeabb52d9275ac83be635306997b7c353727cd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02 17:15:40 +01:00
Manish Pandey d985cb743b Merge "fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif" into integration 2021-07-28 11:29:32 +02:00
Ming Huang 5a5e0aac39 fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif
A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f.
Core put to sleep before its Group enables were cleared.

gicv3_cpuif_disable() will be called in offline core flow.
According to GIC architecture version 3 and version 4:
Architectural execution of a DSB instruction guarantees that
the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,
ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed
by the associated Redistributor.
An ISB or other context synchronization operation must precede
the DSB to ensure visibility of System register writes.

Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
2021-07-23 10:48:00 +08:00
Peng Fan b3c8fd5d77 fix(drivers/scmi-msg): entry: add weak functions
One platform may not implement all the protocols, to avoid build break
when we not include all the protocols, add weak functions.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I1485baa2e8f381cb0eede1a7b93ed10e49934971
2021-07-22 10:27:48 +08:00
Peng Fan 7e4833cdde feat(drivers/scmi-msg): add power domain protocol
Add SCMI power domain protocol, with POWER_STATE_NOTIFY and
POWER_STATE_CHANGE_REQUESTED_NOTIFY not implemented.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ia7c4db57c4c702667f8eaa630c924016e4a8bde0
2021-07-22 10:27:42 +08:00
Peng Fan 0e223c6a9e fix(drivers/scmi-msg): smt: fix build for aarch64
For AARCH64, BIT() will make the number as ULL type, let use BIT_32()
here.

And use %zu for size_t print format.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I1dc18d374cd2c6eb83b40b66ed6189dcc6a21728
2021-07-15 11:51:34 +08:00
Lionel Debieve 9a9ea82948 feat(io_mtd): offset management for FIP usage
A new seek handler is also created. It will be used for NAND to add an
extra offset in case of bad blocks, when FIP is used.

Change-Id: I03fb1588b44029db50583c0b2e7af7a1e88a5a7a
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-07-13 18:16:55 +02:00
Yann Gautier bc3eebb25d feat(nand): count bad blocks before a given offset
In case of FIP, the offsets given in the FIP header are relative.
If bad blocks are found between the FIP base address and this offset,
the offset should be updated, taking care of the bad blocks.

Change-Id: I96fefabb583b3d030ab05191bae7d45cfeefe341
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-07-13 18:16:55 +02:00
Toshiyuki Ogasahara 4379a3e974 feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286
2021-07-10 17:35:36 +02:00
Toshiyuki Ogasahara 726050b8e2 feat(drivers/rcar3): ddr: add function to judge a DDR rank
This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I94d550cea620748f5b15499fed1b791a69d61592
2021-07-10 17:35:32 +02:00
Chiaki Fujii ec767c1b99 fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.41.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168
2021-07-10 17:35:28 +02:00
Toshiyuki Ogasahara b757d3a1d9 fix(drivers/rcar3): i2c_dvfs: fix I2C operation
This commit fixes value to write to the ICCR register according to
the hardware manual.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I1f612a482c012a6739e2f31db80224b222df766c
2021-07-10 17:35:23 +02:00
Toshiyuki Ogasahara 0dae56bb2f fix(drivers/rcar3): fix CPG registers redefinition
This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
2021-07-10 17:35:20 +02:00
Toshiyuki Ogasahara 36d5645aec fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
emmc_registers.h contains redefinition of
CPG_CPGWPR from bl2_cpg_register.h

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ie13590100df08f32193653e50191e66ed42d2b28
2021-07-10 17:35:15 +02:00
Sandrine Bailleux 51018a0558 refactor(measured boot): revisit error handling (3/3)
- In tpm_record_measurement():

   The platform layer is responsible for providing an exhaustive list
   of images to measure. If it doesn't then this should be treated as
   a programming error, as documented in [1].

   Thus, turn the error test into an assertion.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#using-assert-to-check-for-programming-errors

Change-Id: I002309c2ebdf2d348a7d12a8f7f9e82465046b8e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05 10:33:38 +02:00
Sandrine Bailleux 0c83207a55 refactor(measured boot): revisit error handling (2/3)
- In add_event2():

  Turn the first error condition checking whether there is room for an
  extra event2 data structure into an assertion. The platform layer is
  responsible for choosing an appropriate event log buffer size based
  on the number of measurements it expects. If this assertion fires,
  the platform macro EVENT_LOG_SIZE should be adjusted and the
  firmware recompiled.

  Call this assumption out in the function documentation.

  Also remove the second error condition check, which is a subset of
  the first one and thus is redundant.

  As a result of these changes, add_event2() can no longer fail. Thus,
  change its return type from int to void.

  Also, the 'size_of_event' local variable is now unused in release
  builds so remove it and move its value into the assertion.

Change-Id: I113fc141de59708b20435a0c7126255561ab7786
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05 10:33:17 +02:00
Sandrine Bailleux ddb07a5689 refactor(measured boot): revisit error handling (1/3)
- In event_log_init():

   Throughout the function, we are incrementing a pointer by some fixed
   amounts of bytes (corresponding to the size of some data structure or
   to some constant number of bytes), there is no variable-size
   increments in the picture. Thus it seems pointless to verify that the
   pointer has indeed been incremented by this fixed amount of bytes
   afterwards.

   For this reason, remove these checks altogether. As a result, the
   start_ptr local variable is now unused so remove it as well.

Change-Id: I612e2278cd3a63d1417427e45d81e285503f5efe
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05 10:32:55 +02:00
Sandrine Bailleux ef65c9c6d1 style(measured boot): fix incorrect indentation
Change-Id: I5b84a28ed254a7c7bb95c18fa999592a4e3f6d90
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-05 10:19:30 +02:00
Mark Dykes 365e0f7764 Merge changes from topic "st_fixes" into integration
* changes:
  fix(plat/st): correct IO compensation disabling
  fix(plat/st): correct BSEC error code management
  fix(drivers/st/pmic): missing error check
  fix(drivers/st/pmic): initialize i2c_state
  fix(drivers/st/clk): use correct return value
2021-07-01 17:23:30 +02:00
Mark Dykes 156a6e137c Merge "fix(drivers/mtd): macronix quad enable bit issue" into integration 2021-07-01 17:21:07 +02:00
Sandrine Bailleux c04cb15cfa refactor(measured boot): remove weak definition of plat_get_measured_boot_data()
Weak definitions are confusing and should be avoided if possible.
Thus, turn plat_get_measured_boot_data() into a strong definition that
platforms must provide (if they need measured boot).

We could have moved the old weak implementation under plat/common as a
sane, default implementation that platforms may pull in if it suits
them. However, this implementation right now simply measures BL2,
which is not enough to get a complete measured boot flow, so this
patch just removes it.

This change only affects the Arm FVP platform, as no other upstream
platform implements measured boot at the moment.

Change-Id: If8680a39ae0ef1044ee981315439d5e0c8461229
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2021-07-01 10:06:54 +02:00
Mark Dykes ce36b311a6 Merge "fix(drivers/mtd): fix MISRA issues and logic improvement" into integration 2021-06-28 22:15:02 +02:00
Mark Dykes 99ea2e912a Merge "style(scmi_common): add \n to warning messages" into integration 2021-06-28 21:59:41 +02:00
Lionel Debieve c3327408eb fix(drivers/mtd): macronix quad enable bit issue
Invert test logic on the status register control to
fix issue when the bit SR_QUAD_EN_MX is not set.

Change-Id: I8b2f140219f124336bf96462abf9d9445d0308bc
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22 14:10:27 +02:00
Lionel Debieve 5130ad14d5 fix(drivers/mtd): fix MISRA issues and logic improvement
Fix MISRA issues and invert the spi_nor_ready status
to improve readability.
Remove an unneeded variable initialization.

Change-Id: I25a97fbd6c4389156b4f077b986019fa7c30a457
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22 14:10:27 +02:00
Nicolas Le Bayon a4bcfe94e7 fix(drivers/st/pmic): missing error check
In pmic_operate(), "regulators" node value must be checked before
entering in the fdt_for_each_subnode loop.

Change-Id: I1460cd24ec56ec47ab644f396b71b92973e75fb4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22 14:10:27 +02:00
Benjamin Gaignard 42822844bf fix(drivers/st/pmic): initialize i2c_state
Make sure that i2c->i2c_state is correctly initialized
with I2C_STATE_RESET value this avoid hi2c->lock to not
be set to 0 when calling stm32_i2c_init during platform
suspend/resume operations.

Change-Id: I3b4c1f9115589325eb256789a1764c322741db7d
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22 14:10:27 +02:00
Yann Gautier 8f97c4fab1 fix(drivers/st/clk): use correct return value
The function stm32mp1_clk_init() returns an int. Return a negative
error value if the device tree is not found.

Change-Id: I422d5fea46c4d63d55a5b62e1db154c1f53f41b7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-22 14:10:27 +02:00
Madhukar Pappireddy 7cfe5999be Merge changes from topic "io_stm32image" into integration
* changes:
  fix(io_stm32image): invalidate cache on local buf
  refactor(io_stm32image): add header size variable
  fix(io_stm32image): uninitialized variable warning
2021-06-18 15:40:20 +02:00
Heyi Guo ce2b49b879 refactor(gicv3): use helper functions to get SPI/ESPI INTID limit
Use helper functions to get SPI and ESPI INTID limit, to remove
several pieces of similar code in gicv3 driver.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iaf441fe5e333c4260e7f6d98df6fdd931591976d
2021-06-16 09:37:14 +08:00
Heyi Guo 30524ff80a refactor(gicv3): add helper function to get the limit of ESPI INTID
Add helper function gicv3_get_espi_limit() to get the value of
(maximum extended SPI INTID + 1), so that some duplicated code can be
removed later.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I0355ca2647f872e8189add259f6c47d415494cce
2021-06-16 09:24:31 +08:00
Heyi Guo 05579daf79 style(scmi_common): add \n to warning messages
Add newline(\n) to make the message clearer when the warnings are
really triggered.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5e2574a52c9065db32ecb4d453b9b02445f69a82
2021-06-08 20:10:35 +08:00
Heyi Guo 1e9428ea96 refactor(gicv3): add helper function to get the limit of SPI INTID
Add helper function gicv3_get_spi_limit() to get the value of (maximum
SPI INTID + 1), so that some duplicated code can be removed later.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I160c8a88fbb71d22790b8999a84afbfba766f5e7
2021-06-08 19:07:49 +08:00
Madhukar Pappireddy b39a1308ab Merge changes I85a87dc9,If75df769,I55b0c910 into integration
* changes:
  feat(plat/st): add STM32MP_EMMC_BOOT option
  feat(drivers/st): manage boot part in io_mmc
  feat(drivers/mmc): boot partition read support
2021-06-07 18:21:16 +02:00
Manish Pandey 95d064b451 Merge "fix(plat/marvell/armada): select correct pcie reference clock source" into integration 2021-06-07 15:45:30 +02:00
Yann Gautier a5bcf82402 fix(io_stm32image): invalidate cache on local buf
When retrieving data from stm32 image file, the header is removed with
a memcpy that shifts the data to overwrite the useless header for next
binary.

STM32 binary from boot device:
|-------------------------------------|
| header | payload                    |
|-------------------------------------|

After the memcpy:
|-------------------------------------|
| payload                    | remain |
|-------------------------------------|

But the remaining data after the shifted payload is still in
the cache. As it is of no use for anyone, just invalidate the cache
at this address.
This is required if the DDR is mapped secure in BL2, and the secure
access is forbidden in BL33, or else TZC-400 issues an error.

Change-Id: Ice2af3b1ca49eccb79bfc62db60437e259d344ca
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-04 15:15:18 +02:00
Yann Gautier b6561c1217 refactor(io_stm32image): add header size variable
A variable hdr_sz is created in stm32image_partition_read() function.
It just represents the size of the stm32 image header but it really
improves the readability of the function.

Change-Id: I95ec62a78a4b6c6a75b0d8c8aa0faef8bee424da
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-04 15:15:18 +02:00
Nicolas Le Bayon c1d732d0db fix(io_stm32image): uninitialized variable warning
Fixes implementation against build warning reported by GCC:

drivers/st/io/io_stm32image.c: In function ‘stm32image_partition_read’:
drivers/st/io/io_stm32image.c:249:6: error: ‘result’ may be used
uninitialized in this function [-Werror=maybe-uninitialized]
  int result;
      ^~~~~~

Actually, by construction the current implementation of function
stm32image_partition_read() does not mandate result to be initialized
since it always reaches the exit point with a valid value in 'result'.
Yet, this change prevents compiler from complaining and is more robust
against future changes in the implementation.

Change-Id: I383575edb605b7535398952a5fdfc266c0068c71
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-06-04 15:15:18 +02:00
Vyacheslav Yurkov f3d2750aa2 feat(drivers/st): manage boot part in io_mmc
Use dedicated read function for boot partition

Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
Change-Id: If75df7691fce0797205365736fc6e4e3429efdca
2021-06-04 10:08:39 +02:00
Vyacheslav Yurkov 5014b52dec feat(drivers/mmc): boot partition read support
Added a public function to read blocks from a current boot partition.
switch between partitions has to respect eMMC partition switch timing.

Signed-off-by: Vyacheslav Yurkov <uvv.mail@gmail.com>
Change-Id: I55b0c910314253e5647486609583fd290dadd30a
2021-06-04 09:52:37 +02:00
Pali Rohár 5a91c439cb fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
2021-06-02 14:19:52 +01:00
Guo Yi 371648e1c7 fix(plat/marvell/armada): select correct pcie reference clock source
when comphy is in pcie mode, correct reference clock need be
selected according to SAR register that reflect the CPx_MPP boot
strapping pins. Either from external or from internal

Signed-off-by: Guo Yi <yguo@cavium.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Change-Id: I99ed64a141e85174cc0f8e9dab5886ab2506efa1
2021-06-01 17:44:21 +02:00