Commit Graph

908 Commits

Author SHA1 Message Date
dp-arm a440900803 AArch32: Add `TRUSTED_BOARD_BOOT` support
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode.

To build this patch the "mbedtls/include/mbedtls/bignum.h"
needs to be modified to remove `#define MBEDTLS_HAVE_UDBL`
when `MBEDTLS_HAVE_INT32` is defined. This is a workaround
for "https://github.com/ARMmbed/mbedtls/issues/708"

NOTE: TBBR support on Juno AArch32 is not currently supported.

Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-15 16:34:27 +01:00
David Cunado fa715215e7 Add missing SPDX header
A new file added as part of arm-trusted-firmware#927 was missing the
SPDX license identifier - this patch adds the missing identifier.

Change-Id: Id1355f2bdca930b7e65bb54eff7e6c764ebb0d96
Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-11 17:31:29 +01:00
davidcunado-arm d6104f5ab4 Merge pull request #927 from jeenu-arm/state-switch
Execution state switch
2017-05-11 16:04:52 +01:00
dp-arm c3e70be1c1 Use SPDX license identifiers for remaining files
Change-Id: I7f54f45db65f32481cc05e1bd2c9c683b756e19a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-10 15:16:34 +01:00
davidcunado-arm a78b73f804 Merge pull request #918 from rockchip-linux/rk3328
rockchip: rk3328: support rk3328
2017-05-10 12:48:38 +01:00
Antonio Nino Diaz 9bb0b3c667 Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"
This reverts commit b6dcbf588a.

This function wasn't used when it was removed, but it is needed to
compile the new changes proposed for Rockchip platforms.

Change-Id: Ia5bfe1f8398e08431f96923e2f059a83e5cb78d4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-10 11:00:59 +01:00
tony.xie be2a3127a3 rockchip: rk3328: Add a missing paragraph for copyright notice.
Change-Id: I78c7e304d3070f66e2ca3bf838c76ee6a2ae3430
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-05-10 10:26:08 +08:00
Jeenu Viswambharan b10d44995e Introduce ARM SiP service to switch execution state
In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether the lower exception level executes in AArch64 or AArch32 state.
For an exception level to have its execution state changed at run time,
it must request the change by raising a synchronous exception to the
higher exception level.

This patch implements and adds such a provision to the ARM SiP service,
by which an immediate lower exception level can request to switch its
execution state. The execution state is switched if the request is:

  - raised from non-secure world;

  - raised on the primary CPU, before any secondaries are brought online
    with CPU_ON PSCI call;

  - raised from an exception level immediately below EL3: EL2, if
    implemented; otherwise NS EL1.

If successful, the SMC doesn't return to the caller, but to the entry
point supplied with the call. Otherwise, the caller will observe the SMC
returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built
for AArch32, the feature is not supported, and the call will always
fail.

For the ARM SiP service:

  - Add SMC function IDs for both AArch32 and AArch64;
  - Increment the SiP service minor version to 2;
  - Adjust the number of supported SiP service calls.

Add documentation for ARM SiP service.

Fixes ARM-software/tf-issues#436

Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-04 11:00:34 +01:00
dp-arm 82cb2c1ad9 Use SPDX license identifiers
To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-03 09:39:28 +01:00
Jeenu Viswambharan f4c8aa9054 Add macro to check whether the CPU implements an EL
Replace all instances of checks with the new macro.

Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-02 16:11:12 +01:00
davidcunado-arm 7fa3214e18 Merge pull request #896 from sbranden/tf_issue_461
Move defines in utils.h to utils_def.h to fix shared header compile i…
2017-05-02 11:13:20 +01:00
Varun Wadekar 7c1d434206 Tegra210: implement 'get_target_pwr_state' handler
This patch implements the handler to calculate the cluster and
system power states for the Tegra210 SoC. The power states
returned by this handler are used by the PSCI library to decide
cache maintenance operations - cluster v cpu.

Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:36:44 -07:00
Varun Wadekar 14a1c0edf0 Tegra: fix the NS DRAM address calculation logic
This patch fixes the logic used to calculate the end of NS memory
aperture. The functions allows zero sized NS apertures as that is
a valid requirement for some use cases. e.g. VPR resize.

Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:33:44 -07:00
Varun Wadekar 9d42d23a2c Tegra: memctrl_v2: zero out NS Video memory carveout region
The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.

This patch adds the logic to zero out the previous memory carveout
region.

Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:33:31 -07:00
Varun Wadekar e9cb01d96e Tegra186: calculate proper power state for cluster/system power down
Earlier, we were setting "System Suspend" as the power state for all system
states. This caused incorrect system state during a cluster power down.

This patch fixes this anomaly and sets the correct power state during a
cluster/system power down.

Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:29:13 -07:00
Steven Kao ab3a33fe5c Tegra186: mce: max retries for ARI requests
This patch adds max retries for all ARI requests and asserts
if the ARI request is still busy.

Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:28:56 -07:00
Steven Kao e99eeec6ff Tegra: memmap Tegra micro-seconds timer controller
This patch adds the Tegra micro-seconds controller to the
memory map. This allows us to use the delay_timer functionality.

Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:28:44 -07:00
Steven Kao d29d96fb3f Tegra: early init the delay timer
This patch moves the platform delay timer init to early BL31
platform setup, so that platforms can use the udelay/mdelay
routines in the early init code.

Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01 15:27:38 -07:00
Scott Branden 0f22bef31d Merge branch 'integration' into tf_issue_461 2017-04-29 08:36:12 -07:00
Scott Branden 53d9c9c85b Move defines in utils.h to utils_def.h to fix shared header compile issues
utils.h is included in various header files for the defines in it.
Some of the other header files only contain defines.  This allows the
header files to be shared between host and target builds for shared defines.

Recently types.h has been included in utils.h as well as some function
prototypes.

Because of the inclusion of types.h conflicts exist building host tools
abd these header files now.  To solve this problem,
move the defines to utils_def.h and have this included by utils.h and
change header files to only include utils_def.h and not pick up the new
types.h being introduced.

Fixes ARM-software/tf-issues#461

Signed-off-by: Scott Branden <scott.branden@broadcom.com>

Remove utils_def.h from utils.h

This patch removes utils_def.h from utils.h as it is not required.
And also makes a minor change to ensure Juno platform compiles.

Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29
2017-04-29 08:30:05 -07:00
Antonio Nino Diaz bf097cac40 Tegra: Control inclusion of helper code used for asserts
One assert depends on code that is conditionally compiled based on the
DEBUG define. This patch modifies the conditional inclusion of such code
so that it is based on the ENABLE_ASSERTIONS build option.

Change-Id: Ic5659a3db8632593b9d2e83dac6d30afd87c131d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26 13:55:01 -07:00
Varun Wadekar cd3b7eb46a Tegra: smmu: enable asserts by default
This patch enables the assert in the context save routine
by default, for all flavours of the build.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26 13:55:01 -07:00
Varun Wadekar 6c16918f7d Tegra: enable 'ENABLE_ASSERTIONS' for all builds
This patch changes the platform Makefile to set `ENABLE_ASSERTIONS` to
1 instead of the deprecated option `ASM_ASSERTION`. This also pulls in
C assertions in release mode.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26 13:54:30 -07:00
Varun Wadekar 03af25bc9b Tegra: group platform settings together
This patch groups all the platform configuration macros into
the common platform.mk makefile.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-26 13:48:00 -07:00
tony.xie 0d5ec955b8 rockchip: rk3328: support rk3328
rk3328 is a Quad-core soc and Cortex-a53 inside!
This patch supports the following functions:
1、power up/off cpus
2、suspend/resume cpus
3、suspend/resume system
4、reset system
5、power off system

Change-Id: I60687058d13912c6929293b06fed9c6bc72bdc84
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-04-25 11:10:56 +08:00
Soby Mathew abd2aba99e CSS: Allow system suspend only via PSCI SYSTEM_SUSPEND API
The CSS power management layer previously allowed to suspend system
power domain level via both PSCI CPU_SUSPEND and PSCI SYSTEM_SUSPEND
APIs. System suspend via PSCI CPU_SUSPEND was always problematic to
support because of issues with targeting wakeup interrupts to
suspended cores before the per-cpu GIC initialization is done. This
is not the case for PSCI SYSTEM_SUSPEND API because all the other
cores are expected to be offlined prior to issuing system suspend and
PSCI CPU_ON explicit calls will be made to power them on. Hence the Juno
platform used to downgrade the PSCI CPU_SUSPEND request for system
power domain level to cluster level by overriding the default
`plat_psci_pm_ops` exported by CSS layer.

Given the direction the new CSS platforms are evolving, it is best to
limit the system suspend only via PSCI SYSTEM_SUSPEND API for all
CSS platforms. This patch makes changes to allow system suspend
only via PSCI SYSTEM_SUSPEND API. The override of `plat_psci_ops`
for Juno is removed.

Change-Id: Idb30eaad04890dd46074e9e888caeedc50a4b533
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-04-24 12:05:39 +01:00
davidcunado-arm 3fb340a2b4 Merge pull request #912 from vwadekar/tegra-smmu-ctx-save-robust
Tegra: smmu: make the context save sequence robust
2017-04-21 17:43:19 +01:00
davidcunado-arm 484acce376 Merge pull request #910 from dp-arm/dp/AArch32-juno-port
Add AArch32 support for Juno
2017-04-21 17:10:27 +01:00
davidcunado-arm 94e0ed6052 Merge pull request #902 from vwadekar/tegra186-sip-mce-calls
Tegra186: Support AARCH32/64 encoding for MCE calls
2017-04-21 13:57:02 +01:00
davidcunado-arm 228bfabaf8 Merge pull request #903 from antonio-nino-diaz-arm/an/build-xlat-v1
ARM platforms: Add option to use xlat tables lib v1
2017-04-21 09:40:25 +01:00
davidcunado-arm 2edf64827f Merge pull request #906 from antonio-nino-diaz-arm/an/asserts-release
Add `ENABLE_ASSERTIONS` build option
2017-04-21 09:37:36 +01:00
Varun Wadekar 63ac1a2a79 Tegra: smmu: make the context save sequence robust
This patch sanity checks the SMMU context created by the platform
code. The first entry contains the size of the array; which the
driver now verifies before moving on with the save.

This patch also fixes an error in the calculation of the size of
the context that gets copied to TZDRAM.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-20 19:02:21 -07:00
Yatharth Kochar 6f249345e2 AArch32: Add SP_MIN support for JUNO
This patch adds support for SP_MIN on JUNO platform.
The changes include addition of AArch32 assembly files,
JUNO specific SP_MIN make file and miscellaneous changes
in ARM platform files to enable support for SP_MIN.

Change-Id: Id1303f422fc9b98b9362c757b1a4225a16fffc0b
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20 15:05:21 +01:00
Yatharth Kochar 07570d592e Changes to support execution in AArch32 state for JUNO
Following steps are required to boot JUNO in AArch32 state:
1> BL1, in AArch64 state, loads BL2.
2> BL2, in AArch64 state, initializes DDR.
  Loads SP_MIN & BL33 (AArch32 executable)images.
  Calls RUN_IMAGE SMC to go back to BL1.
3> BL1 writes AArch32 executable opcodes, to load and branch
  at the entrypoint address of SP_MIN, at HI-VECTOR address and
  then request for warm reset in AArch32 state using RMR_EL3.

This patch makes following changes to facilitate above steps:
* Added assembly function to carry out step 3 above.
* Added region in TZC that enables Secure access to the
  HI-VECTOR(0xFFFF0000) address space.
* AArch32 image descriptor is used, in BL2, to load
  SP_MIN and BL33 AArch32 executable images.

A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that
controls above changes. By default this flag is disabled.

NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO.

Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20 15:05:21 +01:00
dp-arm 0498343ac0 css: Ensure PSCI system off/reset is not interrupted
If there is a pending interrupt, it is possible for the AP to come out
of the final WFI before SCP has a chance to act on it.  Prevent this
by disabling the GIC CPU interface before issuing a WFI.

Previously, SCP would not wait on WFI before taking an action but
would shut down the core or system regardless.

Change-Id: Ib0bcf69a515d540ed4f73c11e40ec7c863e39c92
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20 15:05:21 +01:00
Antonio Nino Diaz 044bb2faab Remove build option `ASM_ASSERTION`
The build option `ENABLE_ASSERTIONS` should be used instead. That way
both C and ASM assertions can be enabled or disabled together.

All occurrences of `ASM_ASSERTION` in common code and ARM platforms have
been replaced by `ENABLE_ASSERTIONS`.

ASM_ASSERTION has been removed from the user guide.

Change-Id: I51f1991f11b9b7ff83e787c9a3270c274748ec6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-20 09:58:28 +01:00
Varun Wadekar 0741c96bfa Tegra: smmu: fix the size used to save context
This patch fixes the size used to save the context, when the
device enters System Suspend.

Reported by: David Cunado

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-19 11:49:27 -07:00
Antonio Nino Diaz 3b211ff571 ARM platforms: Add option to use xlat tables lib v1
ARM platforms have migrated to the translation tables library v2.
However, for testing purposes, it can be useful to temporarily switch
back to the old version.

This patch introduces the option `ARM_XLAT_TABLES_LIB_V1`, that switches
to v1 of the library when is set to 1. By default, it is 0, so that ARM
platforms use the new version unless specifically stated.

Updated User Guide.

Change-Id: I53d3c8dd97706f6af9c6fca0364a88ef341efd31
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-19 11:56:08 +01:00
Varun Wadekar c76c1b71ab Tegra186: Support AARCH32/64 encoding for MCE calls
On Tegra systems, there are multiple software components that
require to interact with MCE. The components can either be 32-bit
or 64-bit payloads. This patch supports MCE SMC functions ID for
AARCH32 and AARCH64 architectures to support such clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-17 11:54:33 -07:00
davidcunado-arm 3d21c9452d Merge pull request #899 from vwadekar/tegra186-platform-support-v6
Tegra186 platform support v6
2017-04-16 16:20:38 +01:00
davidcunado-arm ea69a93e72 Merge pull request #890 from masahir0y/scp
Build: add generic way to include SCP_BL2 into FIP image
2017-04-14 01:49:34 +01:00
davidcunado-arm 5d385355f1 Merge pull request #897 from vwadekar/memctrl-v1-xlat-table-v2
Tegra: memctrl_v1: enable 'xlat_table_v2' library
2017-04-14 01:36:12 +01:00
Anthony Zhou 50e91633ee Tegra: fix trivial misra issues
Not having U or ULL as a suffix for these enums causes
a lot of unnecessary MISRA issues. This patch adds U or
ULL suffix to these common enums to reduce number of
MISRA issues.

Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 14:18:42 -07:00
Varun Wadekar e87dac6b45 Tegra: no need to re-init the same console
This patch stops initialising the same UART console, as a "crash"
console. The normal and the crash consoles use the same UART port
and hence the crash console init function now only checks if the
console is ready to be used.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 14:18:42 -07:00
Vignesh Radhakrishnan a9e0260c77 Tegra: Add support for fake system suspend
This patch adds support for fake system suspend (SC7).
This is a debug mode, to ensure that a different code path is
executed for cases like pre-silicon development, where a
full-fledged SC7 is not possible in early stages.

This particular patch ensures that, if fake system suspend is
enabled (denoted by tegra_fake_system_suspend variable
having a non-zero value), instead of calling WFI, a request
for a warm reset is made for starting the SC7 exit procedure.

This ensures that the code path of kernel->ATF and back to
kernel is executed without depending on other components
involved in SC7 code path.

Additionally, this patch also adds support for SMC call
from kernel, enabling fake system suspend mode.

Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 14:18:42 -07:00
Varun Wadekar 62bfc44b3f Tegra: memctrl_v2: restore MC_TXN_OVERRIDE settings
This patch restores the MC_TXN_OVERRIDE settings when we exit from
System Suspend.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 14:16:25 -07:00
Varun Wadekar 0c2276e35f Tegra: memctrl_v1: disable AHB redirection after cold boot
During boot, USB3 and flash media (SDMMC/SATA) devices need access to
IRAM. Because these clients connect to the MC and do not have a direct
path to the IRAM, the MC implements AHB redirection during boot to allow
path to IRAM. In this mode, accesses to a programmed memory address aperture
are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
initialized to disable this aperture. Once bootup is complete, we must
program IRAM base/top, thus disabling access to IRAM.

This patch provides functionality to disable this access. The tegra port
calls this new function before jumping to the non-secure world during
cold boot.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 14:16:25 -07:00
Varun Wadekar cd3de4326b Tegra: platform: support Tegra186 chip id
This patch adds support to read the chip id and identify if
the current platform is Tegra186.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 14:16:14 -07:00
Pritesh Raithatha 95a7fae42c Tegra: memctrl_v2: MC transaction overrides for newer chips
This patch programs MC transaction overrides settings using
mc_txn_override_cfgs array for all Tegra chips beyond Tegra186
rev. A01

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-13 12:35:27 -07:00
Stephen Warren 7b3052710b Tegra186: mce: Avoid implementation-defined bitfield types
GCC version 4.8 (and presumably earlier) warn when non-standard types are
used for bitfield definitions when -pedantic is enabled. This prevents TF
from being built with such toolchains, since -Werror -pedantic options are
used.

gcc-4.9 removed this warning; -pedantic is intended to cause gcc to emit a
warning in all cases required by the standard, but the standard does not
require a warning in this case.

See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57773

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2017-04-13 12:35:21 -07:00