This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry in the plat_arm_mmap[] array and avoids to map extra memory when
it's not needed.
Change-Id: I6ae60822ff8f0de198145925b0b0d45355179a94
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`assert()` will not generate the strings implied in the expression taken
as parameter. This allows to save some memory when Juno is built for
LOG_LEVEL = LOG_LEVEL_VERBOSE and DEBUG = 1.
FixesARM-software/tf-issues#511
Change-Id: Id84a40f803ab07a5a8f6e587167af96694a07d04
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of EL3_PAYLOAD_BASE bl2_platform_setup was
calling zero_normalmem with device memory and it generated an abort.
Change-Id: If013603f209a12af488a9c54481f97a8f395b26a
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch renames this macro for clarity.
Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register.
Since ACTLR and ACTRL_EL1 are different registers this patch renames
these constants for clarity.
Change-Id: I2a9e402dab7b0fcb6e481ee0d8a11eda943ed299
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
The current definition of ARM_INSTANTIATE_LOCK macro includes a
semicolon, which means it's omitted where it's used. This is anomalous
for a C statement in global scope.
Fix this by removing semicolon from the definition; and where it's a
NOP, declare a file-scoped variable explicitly tagged as unused to avoid
compiler warning.
No functional changes.
Change-Id: I2c1d92ece4777e272a025011e03b8003f3543335
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
when shutdown logic power rail, the some sgrf register
value will reset, so need to reinitilize secure.
Change-Id: I8ad0570432e54441fe1c60dd2960a81fd58f7163
Signed-off-by: Lin Huang <hl@rock-chips.com>
we will use timer in pmusarm, when logic power rail shutdown,
the secure timer will gone, so need to initial it in pmusram.
Change-Id: I472e7eec3fc197f56223e6fff9167556c1c5e3bc
Signed-off-by: Lin Huang <hl@rock-chips.com>
we do not have enough pmusram space now, so use slice1 to restore
ddr slice1 ~ slice4, that's will save more pmusram space.
Change-Id: Id54a7944f33d01a8f244cee6a8a0707bfe4d42da
Signed-off-by: Lin Huang <hl@rock-chips.com>
pd_alive control cru, grf, timer, gpio and wdt, when
turn off logic power rail, these register value will
back to reset value, we need to save them value in suspend
and restore them when resuem, since timer will reinitial
in kernel, so it not need to save/restore.
Change-Id: I0fc2a011d3cdc04b66ffbf728e769eb28b51ee38
Signed-off-by: Lin Huang <hl@rock-chips.com>
At the system boot time we need enable watchdog reset, otherwise after
the watchdog is timeout it cannot reset the SoC. We need set the bit 0
and bit 16 together, the bit 16 is mask bit so after set bit 16 we have
permission to operate bit 0 and bit 0 is watchdog reset enabling bit.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
when shutdown logic power rail, the uart register value will reset,
so need to reinitilize debug uart.
Change-Id: I48d3535c0068fd671dea6ea32e908612992faf62
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
If SPD_opteed is defined map ARM_OPTEE_PAGEABLE_LOAD_MEM in bl2 to
allow loading of OP-TEE paged part.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
OP-TEE may have extra images to be loaded. Load them one by one and do
the parsing. In this patch, ARM TF need to load up to 3 images for
OP-TEE: header, pager and pages images. Header image is the info about
optee os and images. Pager image include pager code and data. Paged
image include the paging parts using virtual memory.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change to compile with new plat/common/plat_psci_common.c instead of the old
deprecated plat/common/aarch64/plat_psci_common.c
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Replaces the deprecated ADDR_SPACE_SIZE with PLAT_PHY_ADDR_SPACE_SIZE
and PLAT_VIRT_ADDR_SPACE_SIZE.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
At present, the MPIDR validation on FVP relies on MT bit set along
with shifted affinities. This currently is additionally dependent
on the FVP model being of variant C. This however should be based
on the presence of MT bit alone.
This patch makes the change to always assume that the affinities
are shifted in the FVP model when MT bit is present.
Change-Id: I09fcb0126e1b38d29124bdeaf3450a60b95d485d
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
The nor_XXXXX functions may fail due to different reasons, and it
is convenient to do a full check to detect any failure. It is also
a good idea to have a specific function to do a full status check,
because new checks can be added to this function and they will be
incorporated automatically to any function calling it.
Change-Id: I54fed913e37ef574c1608e94139a519426348d12
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
NOR memory only supports setting bits to 1. To clear a bit, set to zero,
the NOR memory needs to be erased.
Change-Id: Ia82eb15a5af9a6d4fc7e5ea2b58e6db87226b351
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
The status register bits remain until explicitly cleared, which means
that a command can be incorrectly considered to have generated an error -
for example, after reset the status register contents may be unknown or
if a previous command had failed.
This patch clears the status register before beginning any command to
be sure that the status register only represents information about the
current operation.
Change-Id: I9e98110ee24179937215461c00b6543a3467b350
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
lock/unlock operation must wait until WSM bit
is set. Since we do not allow to loop forever then these functions
must return an error if WSM bit isn't enabled after a number of tries.
Change-Id: I21c9e292b514b28786ff4a225128bcd8c1bfa999
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Clear the cpuidle flag when resuming from idle. This flag is set
when entering idle, and if it remains set when resuming, it can
prevent the cluster from powering off during the next system
suspend operation. During system suspend, all CPUs are plugged
out except the last CPU, which is suspended. If any of the
cpuidle flags are set at this point, the last CPU will be stuck
in a WFI loop and will not be powered off.
This problem only occurs during system suspend.
Signed-off-by: Tao Wang <kevin.wangtao@linaro.org>
The generic LOAD_IMAGE_V2 framework has been merged and enable for almost
all the arm platform. Because qemu platform doesn't share those common
files with arm, QEMU haven't got this support yet.
This patch add all the necessary code the files for adding LOAD_IMAGE_V2
support on QEMU and enable it as default.
FixesARM-software/tf-issues#507
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:
.align X
myfunction:
However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.
An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:
[...]
endfunc plat_crash_console_putc
.align 16
func platform_cpu_warmboot
[...]
This assembles into the following plat_helpers.o:
Sections:
Idx Name Size [...] Algn
9 .text.plat_crash_console_putc 00010000 [...] 2**16
10 .text.platform_cpu_warmboot 00000080 [...] 2**3
As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).
There's no real way to fix this with the existing func macro. Code like
func myfunc
.align X
happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.
Also fix up all existing instances of this dangerous antipattern.
Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to 3 images
for optee os: header, pager and paged images. Header image is the info
about optee os and images. Pager image include pager code and data.
Paged image include the paging parts using virtual memory.
Change-Id: Ia3bcfa6d8a3ed7850deb5729654daca7b00be394
Signed-off-by: Summer Qin <summer.qin@arm.com>
Since Trusted OS firmware may have extra images, need to
assign new uuid and image id for them.
The TBBR chain of trust has been extended to add support
for the new images within the existing Trusted OS firmware
content certificate.
Change-Id: I678dac7ba1137e85c5779b05e0c4331134c10e06
Signed-off-by: Summer Qin <summer.qin@arm.com>
Revision C of the Base FVP has the same memory map as earlier revisions,
but has the following differences:
- Implements CCI550 instead of CCI400,
- Has a single instantiation of SMMUv3,
- CPU MPIDs are shifted left by one level, and has MT bit set in them.
The correct interconnect to program is chosen at run time based on the
FVP revision. Therefore, this patch implements FVP functions for
interconnect programming, rather than depending on ARM generic ones. The
macros used have been renamed to reflect this change.
Additionally, this patch initializes SMMUv3 as part of FVP early
platform setup.
New ARM config flags are introduced for feature queries at run time.
Change-Id: Ic7b7f080953a51fceaf62ce7daa6de0573801f09
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
The CCI crash dump macros assumes CCI base at build time. Since this
can't be the case for CCI on FVP, choose not to register dump CCI
registers for FVP.
Change-Id: I7374a037e7fd0a85b138e84b3cf0aa044262da97
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
ARM CPUs with multi-threading implementation has more than one
Processing Element in a single physical CPU. Such an implementation will
reflect the following changes in the MPIDR register:
- The MT bit set;
- Affinity levels pertaining to cluster and CPUs occupy one level
higher than in a single-threaded implementation, and the lowest
affinity level pertains to hardware threads. MPIDR affinity level
fields essentially appear shifted to left than otherwise.
The FVP port henceforth assumes that both properties above to be
concomitant on a given FVP platform.
To accommodate for varied MPIDR formats at run time, this patch
re-implements the FVP platform-specific functions that translates MPIDR
values to a linear indices, along with required validation. The same
treatment is applied for GICv3 MPIDR hashing function as well.
An FVP-specific build option FVP_MAX_PE_PER_CPU is introduced which
specifies the maximum number of threads implemented per CPU. For
backwards compatibility, its value defaults to 1.
Change-Id: I729b00d3e121d16ce9a03de4f9db36dfac580e3f
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
plat_get_my_stack is called from C, so it can't expect argument
registers to be preserved. Stash registers temporarily onto the stack
instead.
plat_set_my_stack is called during early init, when there exists no
stack. Use any register other than argument registers to stash temporary
values.
Change-Id: I98052e20671d0933201d45ec7a5affccd71ce08c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
danh-arm
Sandrine Bailleux
Soby Mathew
Roberto Vargas
Eleanor Bonnici
Jeenu Viswambharan
Lin Huang
Leo Yan
davidcunado-arm
Jens Wiklander
Isla Mitchell
Tao Wang
Fu Wei
Julius Werner
Summer Qin