Update SPM's threat model to contain threats related to notifications
feature, compliant with FF-A v1.1 spec.
Change-Id: I4a825be5dd14137a0d04d532adfe5343714794c5
Signed-off-by: J-Alves <joao.alves@arm.com>
For future reference, this changelog was generated with the following
command:
npm run release -- --skip.commit --skip.tag --release-as 2.6.0
Change-Id: Idf6be5c3be15ddfdb1d32fafb9e0e4b399b269f3
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
- Overview of FF-A v1.1 notifications feature, and list of all
the new related interface.
- FFA_RXTX_UNMAP now implemented, so provided description.
- FF-A v1.1 interfaces documented: FFA_SPM_ID_GET and
FFA_SECONDARY_EP_REGISTER.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If40b4d2b2473f81ecfb2ddbf14852c3f10682867
This change adds a new documentation page describing the commit style,
acceptable Conventional Commits types and scopes, and documents the
process for expanding the list of scopes.
Change-Id: Iad957b67fa71a879e8aa0790c58a5b08cec300d6
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change introduces a new NPM run script to automatically generate
the release changelog, as well as bump version numbers across the
code-base and create the release tag.
This script runs [Standard Version] to execute this, which is a tool
designed around automating substantial parts of the release process.
This can be done by running:
npm run release -- [<standard-version args>]
Standard Version expects the project to adhere to the [Semantic
Versioning] convention which TF-A does not, so you may need to specify
the version manually, e.g.:
npm run release -- --release-as 2.6.0
Individual steps of the release process may also be skipped at-will,
which may be necessary when, for example, tweaking the changelog:
npm run release -- --skip.commit --skip.tag
Standard Version is configured by the `.versionrc.js` file, which
contains information about the Conventional Commits types and scopes
used by the project, and how they map to the changelog.
To maintain continuity with the existing changelog style - at least to
the extent possible in the move from manual to automatic creation - a
customized changelog template has been introduced, based on the
Conventional Commits template provided by Standard Version.
This template package extends the Conventional Commits template package
by introducing support for parsing the Conventional Commits scopes into
changelog sections, similarly to how they were previously organized.
[Standard Version]:
https://github.com/conventional-changelog/standard-version
[Semantic Versioning]: https://semver.org
Change-Id: I5bafa512daedc631baae951651c38c1c62046b0a
Signed-off-by: Chris Kay <chris.kay@arm.com>
This changes adds support for building Markdown documentation into
Sphinx with [MyST]. We'll make use of this in a later patch, where we
introduce automatically-generated Markdown documentation that needs to
be compiled as part of the Sphinx documentation.
[MyST]: https://myst-parser.readthedocs.io/en/latest
Change-Id: I2a241a588c579fac1a81e1853479908928be1fc8
Signed-off-by: Chris Kay <chris.kay@arm.com>
Updates the Node.js version installed by the prerequisite instructions
from v14 to v16, which is the latest LTS release.
The instructions for installing the Node Version Manager (NVM) have
also been updated for v0.39.0 (previously v0.38.0).
Change-Id: I85528b3906305914ba6169b4dc5aafcf5b36a339
Signed-off-by: Chris Kay <chris.kay@arm.com>
Updates the Python dependencies used to build the project's Sphinx
documentation to their latest versions.
Change-Id: I8baee89c85179a667a3850a7b9705ab76f4d702a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Recently some of our dependencies' dependencies have come into conflict
and are now causing errors when trying to install the Python
requirements. This change introduces `requirements.in` - a list of our
own direct dependencies, and pins them to specific versions.
The existing `requirements.txt` file is now automatically generated by
the `pip-compile` tool - part of the pip-tools package - and ensures
that our dependency tree is also pinned. This is a manual process at
present, but our dependencies are updated infrequently enough that it's
not introducing any major overhead.
Change-Id: I3cd0c11a1a4eccaf0d77b538cfdb94474833b811
Signed-off-by: Chris Kay <chris.kay@arm.com>
In this change the `FFA` substitution has been renamed to `FF-A`, as
well as the term it substitutes to - the `FFA` term does not exist.
Change-Id: I0c33d00d82a5498f7088e6a2b088a0006dfe7f65
Signed-off-by: Chris Kay <chris.kay@arm.com>
As spm_mm cannot handle SVE/SME usage in NS world so its better to give
compilation error when ENABLE_SVE_FOR_NS=1 or ENABLE_SME_FOR_NS=1.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I69dbb272ca681bb020501342008eda20d4c0b096
This patch expands the RME documentation with description of TF-A
changes for RME. It also modifies some other parts of TF-A documentation
to account for RME changes.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9e6feeee235f0ba4b767d239f15840f1e0c540bb
This patch adds some documentation for the GPT library as well as adds
code owners for it.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If1cd79626eadb27e1024d731b26ee2e20af74a66
This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable
SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions
in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these
traps, but support for SME context management does not yet exist in
SPM so building with SPD=spmd will fail.
The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot
be used with SME as it is a superset of SVE and will enable SVE and
FPU/SIMD along with SME.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
Add documentation to build and run a PoC based on the OP-TEE toolkit
to show how TF-A Measured Boot can interact with a third party (f)TPM
service.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I11ac99c4ff54ea52aba0731aa7f707d7cd0c4216
Neoverse V1 erratum 2216392 is a Cat B erratum present in the V1 core.
It applies to revisions r1p0 and r1p1 and is still open. The issue is
also present in r0p0 but there is no workaround in that revision.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic2f90d79c75e8ffef01aac81eddf1bfd8b7164ab
This patch adds a brief description of S-EL0 partition support in the
SPMC using ARMv8.1 FEAT_VHE.
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: Ie079265476604f62d5f2a66684f01341000969d0
Cortex A78 erratum 2242635 is a Cat B erratum present in the A78 Core.
It applies to revisions r1p0, r1p1, r1p2, and is still open. The issue
is also present in r0p0 but there is no workaround for this revision.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieca024254cabbc683ff13a70f3aeb8f2f3c5ce07
Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add
Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[17] to 1'b1 followed by setting few
system control registers to specific values as per attached
SDEN document.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649
Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[13] to 1'b1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720
Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I442be81fbc32e21fed51a84f59584df17f845e96
Update supported models list according to changes for v2.6 release in
ci/tf-a-ci-scripts repository:
* general FVP model update: d10c1b9
* gic600 update: aa2548a
* CSS prebults model update: f1c3a4f
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: If2841f05238facb3cace7d5c8a78083d54f35e27
MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 and Cortex-A510 cores.
MPMM allows the SoC firmware to detect and limit high activity events
to assist in SoC processor power domain dynamic power budgeting and
limit the triggering of whole-rail (i.e. clock chopping) responses to
overcurrent conditions.
This feature is enabled via the `ENABLE_MPMM` build option.
Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or
by via the plaform-implemented `plat_mpmm_topology` function.
Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change makes AMU auxiliary counters configurable on a per-core
basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`.
Auxiliary counters can be described via the `HW_CONFIG` device tree if
the `ENABLE_AMU_FCONF` build option is enabled, or the platform must
otherwise implement the `plat_amu_topology` function.
A new phandle property for `cpu` nodes (`amu`) has been introduced to
the `HW_CONFIG` specification to allow CPUs to describe the view of
their own AMU:
```
cpu0: cpu@0 {
...
amu = <&cpu0_amu>;
};
```
Multiple cores may share an `amu` handle if they implement the
same set of auxiliary counters.
AMU counters are described for one or more AMUs through the use of a new
`amus` node:
```
amus {
cpu0_amu: amu-0 {
#address-cells = <1>;
#size-cells = <0>;
counter@0 {
reg = <0>;
enable-at-el3;
};
counter@n {
reg = <n>;
...
};
};
};
```
This structure describes the **auxiliary** (group 1) AMU counters.
Architected counters have architecturally-defined behaviour, and as
such do not require DTB entries.
These `counter` nodes support two properties:
- The `reg` property represents the counter register index.
- The presence of the `enable-at-el3` property determines whether
the firmware should enable the counter prior to exiting EL3.
Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change adds some documentation on the AMU and its purpose. This is
expanded on in later patches.
Change-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01
Signed-off-by: Chris Kay <chris.kay@arm.com>
This change reduces preprocessor dependencies on the
`AMU_GROUP1_NR_COUNTERS` and `AMU_GROUP1_COUNTERS_MASK` definitions, as
these values will eventually be discovered dynamically.
In their stead, we introduce the `ENABLE_AMU_AUXILIARY_COUNTERS` build
option, which will enable support for dynamically detecting and
enabling auxiliary AMU counters.
This substantially reduces the amount of memory used by platforms that
know ahead of time that they do not have any auxiliary AMU counters.
Change-Id: I3d998aff44ed5489af4857e337e97634d06e3ea1
Signed-off-by: Chris Kay <chris.kay@arm.com>
With the introduction of MPMM, the auxiliary AMU counter logic requires
refactoring to move away from a single platform-defined group 1 counter
mask in order to support microarchitectural (per-core) group 1 counters.
BREAKING CHANGE: The `PLAT_AMU_GROUP1_COUNTERS_MASK` platform definition
has been removed. Platforms should specify per-core AMU counter masks
via FCONF or a platform-specific mechanism going forward.
Change-Id: I1e852797c7954f92409222b066a1ae57bc72bb05
Signed-off-by: Chris Kay <chris.kay@arm.com>
there are features which are marked as experimental even though they
are stable and used for quite some time.
Following features are no longer marked as experimental
- SPMD
- MEASURED_BOOT
- FCONF and associated build flags
- DECRYPTION_SUPPORT and associated build flags
- ENABLE_PAUTH
- ENABLE_BTI
- USE_SPINLOCK_CAS
- GICv3 Multichip support
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I4bb653d9c413c66095ec31f0b8aefeb13ea04ee9
When building a FIP with OP-TEE as BL32 on STM32MP1, AARCH32_SP=optee
has to be added to the make command.
Change-Id: I900c01957fe4ed7ed13ca955edd91ed1c5c5c4fa
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com
We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)
Change-Id: I673e0dce8eb3ca3a004a43158a948431b032e93a
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Making tb_fw_config ready to pass the Event Log base address
and size information to BL2.
Change-Id: I5dd0e79007e3848b5d6d0e69275a46c2e9807a98
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add support for Globalscale MOCHAbin board.
Its based on Armada 7040 SoC and ships in multiple DRAM options:
* 2GB DDR4 (1CS)
* 4GB DDR4 (1CS)
* 8GB DDR4 (2CS)
Since it ships in multiple DRAM configurations, an
Armada 3k style DDR_TOPOLOGY variable is added.
Currently, this only has effect on the MOCHAbin, but
I expect more boards with multiple DRAM sizes to be
supported.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305
* changes:
refactor(gpt): productize and refactor GPT library
feat(rme): disable Watchdog for Arm platforms if FEAT_RME enabled
docs(rme): add build and run instructions for FEAT_RME
fix(plat/fvp): bump BL2 stack size
fix(plat/fvp): allow changing the kernel DTB load address
refactor(plat/arm): rename ARM_DTB_DRAM_NS region macros
refactor(plat/fvp): update FVP platform DTS for FEAT_RME
feat(plat/arm): add GPT initialization code for Arm platforms
feat(plat/fvp): add memory map for FVP platform for FEAT_RME
refactor(plat/arm): modify memory region attributes to account for FEAT_RME
feat(plat/fvp): add RMM image support for FVP platform
feat(rme): add GPT Library
feat(rme): add ENABLE_RME build option and support for RMM image
refactor(makefile): remove BL prefixes in build macros
feat(rme): add context management changes for FEAT_RME
feat(rme): add Test Realm Payload (TRP)
feat(rme): add RMM dispatcher (RMMD)
feat(rme): run BL2 in root world when FEAT_RME is enabled
feat(rme): add xlat table library changes for FEAT_RME
feat(rme): add Realm security state definition
feat(rme): add register definitions and helper functions for FEAT_RME
Olivier Deprez
J-Alves
Manish V Badarkhe
Chris Kay
Manish Pandey
Zelalem Aweke
johpow01
Madhukar Pappireddy
Joanna Farley
Javier Almansa Sobrino
Raghu Krishnamurthy
nayanpatel-arm
Maksims Svecovs
Sandrine Bailleux
Yann Gautier
Daniel Boulby
Robert Marko
Mark Dykes
Bipin Ravi
Soby Mathew