Commit Graph

2097 Commits

Author SHA1 Message Date
Madhukar Pappireddy 866e6721f3 Merge changes from topic "scmi_v2_0" into integration
* changes:
  drivers/arm/css/scmi: Update power domain protocol version to 2.0
  tc0: update GICR base address
2021-04-15 23:39:31 +02:00
Nicola Mazzucato b67e9880fc drivers/arm/css/scmi: Update power domain protocol version to 2.0
The SCMI power domain protocol in firmware has been updated to v2.0,
thus update the corresponding version in TF-A too.

Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
2021-04-14 12:13:26 +01:00
Madhukar Pappireddy 511c7f3a9d Merge changes from topic "dcc_console" into integration
* changes:
  plat:xilinx:versal: Add JTAG DCC support
  plat:xilinx:zynqmp: Add JTAG DCC support
  drivers: dcc: Support JTAG DCC console
2021-04-13 21:42:55 +02:00
Madhukar Pappireddy 29e11bb299 Merge "driver: brcm: add USB driver" into integration 2021-04-12 16:44:11 +02:00
Madhukar Pappireddy bab737d397 Merge "driver: brcm: add mdio driver" into integration 2021-04-12 16:43:48 +02:00
Olivier Deprez 9fa849d36e Merge "arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms" into integration 2021-04-12 15:37:14 +02:00
Olivier Deprez e729595fa9 Merge "Fix: Remove save/restore of EL2 timer registers" into integration 2021-04-07 21:25:26 +02:00
Max Shvetsov a7cf2743f3 Fix: Remove save/restore of EL2 timer registers
Since there is a secure and non-secure version of the timer registers
there is no need to preserve their context in EL3.
With that, following registers were removed from EL3 save/restore
routine:
	cnthps_ctl_el2
	cnthps_tval_el2
	cnthps_cval_el2
	cnthvs_ctl_el2
	cnthvs_tval_el2
	cnthvs_cval_el2
	cnthp_ctl_el2
	cnthp_cval_el2
	cnthp_tval_el2
	cnthv_ctl_el2
	cnthv_cval_el2
	cnthv_tval_el2

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
2021-04-07 11:18:23 +01:00
Venkatesh Yadav Abbarapu e5936205ae drivers: dcc: Support JTAG DCC console
The legacy console is gone. Re-add DCC console support based
on the multi-console framework.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
2021-03-31 21:59:45 -06:00
Bipin Ravi 0a144dd4ea Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
2021-03-31 16:02:35 -05:00
bipin.ravi e5fa7459ed Merge "Add Makalu ELP CPU lib" into integration 2021-03-29 22:41:29 +02:00
Sandrine Bailleux 27d593ad95 Merge changes from topic "tzc400_stm32mp" into integration
* changes:
  stm32mp1: add TZC400 interrupt management
  stm32mp1: use TZC400 macro to describe filters
  tzc400: add support for interrupts
2021-03-29 18:20:58 +02:00
Bharat Gooty 48c6a6b650 driver: brcm: add i2c driver
Broadcom I2C controller driver. Follwoing API's are supported:-
- i2c_init() Intialize ethe I2C controller
- i2c_probe()
- i2c_set_bus_speed() Set the I2C bus speed
- i2c_get_bus_speed() Get the current bus speed
- i2c_recv_byte() Receive one byte of data.
- i2c_send_byte() Send one byteof data
- i2c_read_byte() Read single byte of data
- i2c_read() Read multiple bytes of data
- i2c_write_byte Write single byte of data
- i2c_write() Write multiple bytes of data

This driver is verified by reading the DDR SPD data.

Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I2d7fe53950e8b12fab19d0293020523ff8b74e13
2021-03-26 16:22:55 +01:00
johpow01 cb090c1924 Add Makalu ELP CPU lib
Add basic support for Makalu ELP processor core.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93
2021-03-24 12:53:18 -05:00
Pankaj Gupta 39faa9b291 nxp: adding the smmu driver
NXP SMMU driver API for NXP SoC.
- Currently it supports by-passing SMMU, called only when NXP CAAM
is enabled.
- (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ)
  advertised by a bus master for a given transaction.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331
2021-03-24 09:49:31 +05:30
Kuldeep Singh b525a8f0d2 nxp: add flexspi driver support
Flexspi driver now introduces read/write/erase APIs for complete flash
size, FAST-READ are by default used and IP bus is used for erase, read
and write using flexspi APIs.

Framework layer is currently embedded in driver itself using flash_info
defines.

Test cases are also added to confirm flash functionality currently under
DEBUG flag.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
2021-03-24 09:49:31 +05:30
Pankaj Gupta 447a42e735 NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
2021-03-24 09:49:31 +05:30
Pankaj Gupta 3527d6d21d tools: add mechanism to allow platform specific image UUID
Generic framework is added to include platform defined UUID.

This framework is added for the following:
- All NXP SoC based platforms needed additional fip-fuse.bin
- NXP SoC lx2160a based platforms requires additional fip-ddr.bin

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ibe05d9c596256e34077287a490dfcd5b731ef2cf
2021-03-24 09:49:31 +05:30
Pankaj Gupta 18644159a6 tbbr-cot: conditional definition for the macro
Conditional definition for the macro MAX_NUMBER_IDS.

This will allow to update this definition by the platform
specific implementation.

Since, NXP SoC lx2160a based platforms requires additional
FIP DDR to be loaded before initializing the DDR.

It requires addition of defines for DDR image IDs.
A dedicated header plat_tbbr_img_def.h is added to the platform
folder - plat/nxp/common/include/default/

Inclusion of this header file will depend on the compile time
flag PLAT_TBBR_IMG_DEF.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I4faba74dce578e2a34acbc8915ff75d7b8368cee
2021-03-24 09:49:31 +05:30
Pankaj Gupta ff67fca5ac tbbr-cot: fix the issue of compiling time define
Incorrect value is picked for TF_MBEDTLS_USE_RSA defination,
even if the TF_MBEDTLS_RSA is enabled.

Due to which PK_DER_LEN is defined incorrectly.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2ca4ca121e0287b88ea689c885ddcd45a34a3e91
2021-03-24 09:49:31 +05:30
Pankaj Gupta b94bf967e6 cert_create: updated tool for platform defined certs, keys & extensions
Changes to 'tools/cert_create' folder, to include platform defined
certificates, keys, and extensions.

NXP SoC lx2160a : based platforms requires additional
FIP DDR to be loaded before initializing the DDR.

To enable chain of trust on these platforms, FIP DDR
image needs to be authenticated, additionally.

Platform specific folder 'tools/nxp/cert_create_helper'
is added to support platform specific macros and definitions.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I4752a30a9ff3aa1d403e9babe3a07ba0e6b2bf8f
2021-03-24 09:49:31 +05:30
Yann Gautier 34c1a1a43c tzc400: add support for interrupts
A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is enabled, more information about the faulty access
(address, NSAID, type of access) is displayed.

Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-03-23 13:06:15 +01:00
Tomas Pilar e831923f95 tools_share/uuid: Add EFI_GUID representation
The UEFI specification details the represenatation
for the EFI_GUID type. Add this representation to the
uuid_helper_t union type so that GUID definitions
can be shared verbatim between UEFI and TF-A header
files.

Change-Id: Ie44ac141f70dd0025e186581d26dce1c1c29fce6
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
2021-03-18 14:14:22 +01:00
Chris Kay 4e04478aac arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms
The speculation barrier feature (`FEAT_SB`) was introduced with and
made mandatory in the Armv8.5-A extension. It was retroactively made
optional in prior extensions, but the checks in our code-base do not
reflect that, assuming that it is only available in Armv8.5-A or later.

This change introduces the `ENABLE_FEAT_SB` definition, which derives
support for the `sb` instruction in the assembler from the feature
flags passed to it. Note that we assume that if this feature is enabled
then all the cores in the system support it - enabling speculation
barriers for only a subset of the cores is unsupported.

Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: I978ed38829385b221b10ba56d49b78f4756e20ea
2021-03-18 12:34:34 +01:00
Sandrine Bailleux e3ff1766e3 Merge "tzc400: correct FAIL_CONTROL Privileged bit" into integration 2021-03-17 13:51:11 +01:00
Olivier Deprez ae030052a1 Merge changes from topic "od/ffa_spmc_pwr" into integration
* changes:
  SPM: declare third cactus instance as UP SP
  SPMD: lock the g_spmd_pm structure
  FF-A: implement FFA_SECONDARY_EP_REGISTER
2021-03-16 16:15:03 +01:00
Olivier Deprez cdb49d475e FF-A: implement FFA_SECONDARY_EP_REGISTER
Remove the former impdef SPMD service for SPMC entry point
registration. Replace with FFA_SECONDARY_EP_REGISTER ABI
providing a single entry point address into the SPMC for
primary and secondary cold boot.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I067adeec25fc12cdae90c15a616903b4ac4d4d83
2021-03-15 12:29:11 +01:00
Usama Arif 614c14e778
cpus: add Matterhorn ELP ARM cpu library
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607
Signed-off-by: Usama Arif <usama.arif@arm.com>
2021-03-10 16:09:31 +00:00
Bharat Gooty 682fe37032 driver: brcm: add USB driver
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Change-Id: I456aa7a641fffa8ea4e833615af3effec42a31b2
2021-03-10 12:11:26 +05:30
Yann Gautier 4f81ed8e1a tzc400: correct FAIL_CONTROL Privileged bit
When bit 20 of TZC400 Fail control register [1] is set to 1, it means
Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and
FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this.

 [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en

Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-03-08 18:15:26 +01:00
bipin.ravi 8ef06b6cdd Merge "Add Makalu CPU lib" into integration 2021-03-02 16:21:22 +01:00
Manish Pandey ef4c1e19bf Merge "Enable v8.6 AMU enhancements (FEAT_AMUv1p1)" into integration 2021-03-02 10:30:40 +01:00
johpow01 aaabf9789a Add Makalu CPU lib
Add basic support for Makalu CPU.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
2021-03-01 17:11:36 -06:00
Madhukar Pappireddy 174551d598 Merge changes from topic "trng-svc" into integration
* changes:
  plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
  plat/arm: juno: Condition Juno entropy source with CRC instructions
2021-03-02 00:05:10 +01:00
johpow01 873d4241e3 Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0.  This patch enables support for this
feature in EL3 firmware.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
2021-02-25 22:01:59 +00:00
Manish Pandey 8909fa9bbf Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
  plat/marvell/armada: cleanup MSS SRAM if used for copy
  plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
  plat/marvell/armada/common/mss: use MSS SRAM in secure mode
  include/drivers/marvell/mochi: add detection of secure mode
  plat/marvell: fix SPD handling in dram port
  marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
  drivers/marvell/mochi: add support for cn913x in PCIe EP mode
  drivers/marvell/mochi: add missing stream IDs configurations
  plat/marvell/armada/a8k: support HW RNG by SMC
  drivers/rambus: add TRNG-IP-76 driver
2021-02-25 10:43:35 +00:00
Bharat Gooty 441a065aa3 driver: brcm: add mdio driver
Change-Id: Id873670f68a4c584e3b7b586cab28565bb5a1c27
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
2021-02-24 18:05:13 +05:30
Madhukar Pappireddy 1272391ee1 Merge changes Ie5c48303,I5d363c46 into integration
* changes:
  tzc400: adjust filter flag if it is set to FILTER_BIT_ALL
  tzc400: fix logical error in FILTER_BIT definitions
2021-02-22 21:44:01 +00:00
Andre Przywara eb18ce3283 plat/arm: juno: Condition Juno entropy source with CRC instructions
The Juno Trusted Entropy Source has a bias, which makes the generated
raw numbers fail a FIPS 140-2 statistic test.

To improve the quality of the numbers, we can use the CPU's CRC
instructions, which do a decent job on conditioning the bits.

This adds a *very* simple version of arm_acle.h, which is typically
provided by the compiler, and contains the CRC instrinsics definitions
we need. We need the original version by using -nostdinc.

Change-Id: I83d3e6902d6a1164aacd5060ac13a38f0057bd1a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-15 11:55:52 +00:00
Madhukar Pappireddy 94b0c3341e Merge changes from topic "mp/strto_libc" into integration
* changes:
  libc: Import strtoull from FreeBSD project
  libc: Import strtoll from FreeBSD project
  libc: Import strtoul from FreeBSD project
  libc: Import strtol from FreeBSD project
2021-02-11 16:04:54 +00:00
Konstantin Porotchkin c42d5eeaf1 include/drivers/marvell/mochi: add detection of secure mode
Change-Id: I99afc312617df86ae68eb30302203a03877ca748
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/22541
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
2021-02-11 09:43:18 +00:00
Konstantin Porotchkin 6aa9f5d164 drivers/rambus: add TRNG-IP-76 driver
Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver.
This IP is part of Marvell Armada CP110/CP115 die integrated
to Armada 7k/8K/CN913x SoCs

Change-Id: I9c5f510ad6728c7ed168da43d85b19d5852cd873
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
2021-02-11 09:43:18 +00:00
Heyi Guo 3d66ca6d8c tzc400: fix logical error in FILTER_BIT definitions
The filters parameter passed to tzc400_configure_region() is supposed
to be filter bit flag without bit shift, so the macros
TZC_400_REGION_ATTR_FILTER_BIT and TZC_400_REGION_ATTR_FILTER_BIT_ALL
should always construct the value without any shift.

It is not a functional issue for TZC_REGION_ATTR_F_EN_SHIFT is lucky
to be 0.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5d363c462b8517256523f637e670eefa56722afd
2021-02-09 10:41:58 +08:00
Madhukar Pappireddy 8098d54409 Merge "ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask" into integration 2021-02-05 18:33:33 +00:00
Jimmy Brisson 7dfb99118e Add TRNG Firmware Interface service
This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.

Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-05 11:49:18 +00:00
Yann Gautier edaaa98fc5 ddr: stm32mp1_ddr: correct SELFREF_TO_X32 mask
In DDR controller PWRTMG register, the mask for field SELFREF_TO_X32 is
wrong. This field is from bit 16 to 23.

Change-Id: Id336fb08c88f0a153df186dd819e41af72febb88
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-02-04 14:17:32 +01:00
Madhukar Pappireddy d56b957c21 libc: Import strtoull from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy 587c15565f libc: Import strtoll from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy 15c1c14735 libc: Import strtoul from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00
Madhukar Pappireddy 015240d9d3 libc: Import strtol from FreeBSD project
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
The coding guidelines[1] in TF-A forbid the use of ato*() functions
in favour of strto*(). However, the TF-A libc does not provide an
implementation of strto*(), making this rule impossible to satisfy.

Also made small changes to fit into TF-A project. Added the source
files to the libc makefile

[1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution

Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03 10:36:33 -06:00