It's better to have them in a separate file instead of having them spread
across the Makefile. This is what the stack protector is already doing.
Change-Id: Id30742c0af10de5ea6d10674ca25bf52b0f2b262
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
The default Raspberry Pi 3 memory mapping for ATF is geared towards
the use of uboot + Linux. This creates issues when trying to use
ATF with an UEFI payload and Windows on ARM64.
We therefore introduce new build option RPI3_USE_UEFI_MAP, that
enables the build process to use an alternate memory mapping that
is compatible with UEFI + Windows (as well as UEFI + Linux).
FixesARM-software/tf-issues#649
Signed-off-by: Pete Batard <pete@akeo.ie>
Migrate Marvell platforms from legacy console API to
multi-console API.
Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Now that MULTI_CONSOLE_API is enabled for the STM32MP1 platform,
we can remove the non MULTI_CONSOLE_API parts in the driver.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
When compiling assembly files, stdint.h is not included.
UINT32_C and UINT64_C are then not defined.
A new GENMASK macro for assembly is then created.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
According to "openssl" manual:
-K key
The actual key to use: this must be represented as a string
comprised only of hex digits. If only the key is specified,
the IV must additionally specified using the -iv option.
When both a key and a password are specified, the key given
with the -K option will be used and the IV generated from the
password will be taken.
It does not make much sense to specify both key and password.
This patch removes "-k 0" parameter from the encryption command
since we are already using "-K" and "-iv" for the key and IV.
Change-Id: Ia333cedaa3207e643c95d2ec7c229f50eeab96db
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/60745
Reviewed-by: Igal Liberman <igall@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Sharon Habet <sharonh@marvell.com>
The DCDC6 power rail is typically driving VDD_SYS in the SoC, so it is
on by default and uses the default voltage.
As there seems to be at least on board using a different voltage, add
the rail to the list of known voltage lines, so we can setup the right
voltage as early as possible.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The DCDC1 and DCDC5 power rails didn't specify the enable bits. This
isn't critical, since those rails are on by default (and are needed for
every board), but it is inconsistent.
Add the respective enable bits for those two rails.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The DRIVEVBUS pin setup was broken in two ways:
- To configure this pin as an output pin, one has to *clear* the bit in
register 0x8f. It is 0 by default, but rebooting from Linux might have
left this bit set.
- Doing this just configures the pin as an output pin, but doesn't
actually drive power to it. This is done via bit 2 in register 0x30.
Fix the routine to both properly configure the pin and drive power to
it. Add an axp_clrsetbits() helper on the way.
Now this isn't really perfect, still:
We only need to setup the PMIC power rails that are needed for U-Boot.
DRIVEVBUS typically controls the VBUS voltage for the host function of
an USB-OTG port, something we typically don't want in U-Boot (fastboot,
using the USB *device* functionality, is much more common). The
BananaPi-M64 uses the regulator in this way, but the Remix Mini PC
actually controls the power of both its USB ports via this line.
Technically we should differentiate here: if DRIVEVBUS controls a
microUSB-B socket, the power should stay off, any host-type A sockets
should be supplied, though.
For now just always enable the power, that shouldn't really hurt the
USB-OTG functionality anyway.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The legacy Allwinner ATF port used to setup some clocks, and U-Boot is
still relying on this. We don't need to setup the full set, as the SPL
is doing most of it, but it misses one clock (AHB2) and programs another
(AHB1) to quite conservative values.
Fix this up during the platform setup to improve USB and Ethernet
performance, iperf values go up by 31% in my setup with that patch.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The current secure partition design mandates that a) at a point, only
a single core can be executing in the secure partition, and b) a core
cannot be preempted by an interrupt while executing in secure
partition.
Ensure this by activating the SPM priority prior to entering the
parition. Deactivate the priority on return from the
partition.
Change-Id: Icb3473496d16b733564592eef06304a1028e4f5c
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
Register a priority level, PLAT_SP_PRI, for secure partition with EL3
exception handling framework(ehf) module.
The secure partition manager(SPM) would raise the core's priority to
PLAT_SP_PRI before entering the secure partition, to protect the core
from getting interrupted while in secure partition.
Change-Id: I686897f052a4371e0efa9b929c07d3ad77249e95
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
Add a dependency for building EL3 exception handling framework(EHF)
module with the secure partition manager(SPM).
The EHF module is needed for raising the core's running priority
before the core enters the secure partition, and lowering it
subsequently on exit from the secure partition.
Change-Id: Icbe2d0a63f00b46dc593ff3d86b676c9333506c3
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
runtime UART in a manner that prevents the system from rebooting if
ATF tries to send runtime messages there.
Also, we don't want the firmware to share the UART with normal
world, as this can be a DoS attack vector into the secure world.
This patch fixes these 2 issues by introducing new build option
RPI3_RUNTIME_UART, that disables the runtime UART by default.
FixesARM-software/tf-issues#647
Signed-off-by: Pete Batard <pete@akeo.ie>
These issues wer found by sparse:
drivers/st/clk/stm32mp1_clk.c:1524:19:
warning: incorrect type in assignment (different base types)
expected restricted fdt32_t const [usertype] *pkcs_cell
got unsigned int const [usertype] *
plat/st/stm32mp1/plat_image_load.c:13:6:
warning: symbol 'plat_flush_next_bl_params' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:21:16:
warning: symbol 'plat_get_bl_image_load_info' was not declared.
Should it be static?
plat/st/stm32mp1/plat_image_load.c:29:13:
warning: symbol 'plat_get_next_bl_params' was not declared.
Should it be static?
plat/st/stm32mp1/bl2_io_storage.c:40:10:
warning: symbol 'block_buffer' was not declared. Should it be static?
Signed-off-by: Yann Gautier <yann.gautier@st.com>
cppcheck:
[drivers/partition/gpt.c:19] -> [drivers/partition/gpt.c:19]:
(warning) Either the condition 'str_in!=((void*)0)' is redundant
or there is possible null pointer dereference: name.
sparse:
drivers/partition/gpt.c:39:9:
warning: Using plain integer as NULL pointer
Signed-off-by: Yann Gautier <yann.gautier@st.com>
These warnings were issued by sparse:
plat/st/stm32mp1/stm32mp1_pm.c:365:36:
warning: incorrect type in initializer (different modifiers)
expected void ( *[noreturn] pwr_domain_pwr_down_wfi )( ... )
got void ( [noreturn] *<noident> )( ... )
plat/st/stm32mp1/stm32mp1_pm.c:366:23:
warning: incorrect type in initializer (different modifiers)
expected void ( *[noreturn] system_off )( ... )
got void ( [noreturn] *<noident> )( ... )
plat/st/stm32mp1/stm32mp1_pm.c:367:25:
warning: incorrect type in initializer (different modifiers)
expected void ( *[noreturn] system_reset )( ... )
got void ( [noreturn] *<noident> )( ... )
This cannot be changed the other way in all platforms pm drivers
or else there is a compilation error:
plat/st/stm32mp1/stm32mp1_pm.c:234:1: error: attributes should be specified
before the declarator in a function definition
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.
This patch adds Virtual QEMU platform support for
this SoC "versal_virt".
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Switch to the new console APIs enabled by setting MULTI_CONSOLE_API=1.
Enables building with ERROR_DEPRECATED=1.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.
The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.
The exceptions are files that are imported from other projects:
- CryptoCell driver
- dt-bindings folders
- zlib headers
Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently
32-bit values (because they are suffixed with UL and the value
0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When
summing them up, the result overflows the maximum value that can be
encoded in a 32-bit value so it wraps around and does not result in
the expected value.
This patch changes the suffix of these constants into ULL so that they
always are 64-bit values.
Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
This function was needed at the time where we didn't have the
compiler_rt lib. An AArch32-specific variant was provided to handle
the 64-bit shift operation in 32-bit. This is no longer needed.
Change-Id: Ibab709a95e3a723ae2eeaddf873dba70ff2012b3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).
This is to get the __aeabi_llsr() builtin, which is required by a
subsequent patch that uses a logical right shift operator in AArch32.
Change-Id: I9884139a12855a8a87206fb572aaa7dd35582b09
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Imported from the LLVM compiler_rt library on master branch as of
30 Oct 2018 (SVN revision: r345645).
Change-Id: I058cfb5894daf1d12e1ef971c0ba36b0aa089be5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Antonio Niño Díaz
Pete Batard
Ryan Grachek
Konstantin Porotchkin
Yann Gautier
Andre Przywara
Sughosh Ganu
Alexei Colin
Siva Durga Prasad Paladugu
Jerome Forissier
Soby Mathew
Sandrine Bailleux
ldts