Commit Graph

1580 Commits

Author SHA1 Message Date
Alexei Fedorov ed108b5605 Refactor ARMv8.3 Pointer Authentication support code
This patch provides the following features and makes modifications
listed below:
- Individual APIAKey key generation for each CPU.
- New key generation on every BL31 warm boot and TSP CPU On event.
- Per-CPU storage of APIAKey added in percpu_data[]
  of cpu_data structure.
- `plat_init_apiakey()` function replaced with `plat_init_apkey()`
  which returns 128-bit value and uses Generic timer physical counter
  value to increase the randomness of the generated key.
  The new function can be used for generation of all ARMv8.3-PAuth keys
- ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`.
- New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions
  generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively;
  pauth_disable_el1()` and `pauth_disable_el3()` functions disable
  PAuth for EL1 and EL3 respectively;
  `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from
  cpu-data structure.
- Combined `save_gp_pauth_registers()` function replaces calls to
  `save_gp_registers()` and `pauth_context_save()`;
  `restore_gp_pauth_registers()` replaces `pauth_context_restore()`
  and `restore_gp_registers()` calls.
- `restore_gp_registers_eret()` function removed with corresponding
  code placed in `el3_exit()`.
- Fixed the issue when `pauth_t pauth_ctx` structure allocated space
  for 12 uint64_t PAuth registers instead of 10 by removal of macro
  CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h`
  and assigning its value to CTX_PAUTH_REGS_END.
- Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions
  in `msr	spsel`  instruction instead of hard-coded values.
- Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI.

Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-09-13 14:11:59 +01:00
Soby Mathew 2fc6ffc451 Merge "libc: fix sparse warning for __assert()" into integration 2019-09-12 12:34:27 +00:00
Soby Mathew 91624b7fed Merge changes from topic "jc/mte_enable" into integration
* changes:
  Add documentation for CTX_INCLUDE_MTE_REGS
  Enable MTE support in both secure and non-secure worlds
2019-09-12 12:31:22 +00:00
Soby Mathew 684b3a0205 Merge "Add UBSAN support and handlers" into integration 2019-09-12 11:14:21 +00:00
Soby Mathew 9af73b3688 Merge changes from topic "amlogic-refactoring" into integration
* changes:
  amlogic: Fix includes order
  amlogic: Fix header guards
  amlogic: Fix prefixes in the SoC specific files
  amlogic: Fix prefixes in the PM code
  amlogic: Fix prefixes in the SCPI related code
  amlogic: Fix prefixes in the MHU code
  amlogic: Fix prefixes in the SIP/SVC code
  amlogic: Fix prefixes in the thermal driver
  amlogic: Fix prefixes in the private header file
  amlogic: Fix prefixes in the efuse driver
  amlogic: Fix prefixes in the platform macros file
  amlogic: Fix prefixes in the helpers file
  amlogic: Rework Makefiles
  amlogic: Move the SIP SVC code to common directory
  amlogic: Move topology file to common directory
  amlogic: Move thermal code to common directory
  amlogic: Move MHU code to common directory
  amlogic: Move efuse code to common directory
  amlogic: Move platform macros assembly file to common directory
  amlogic: Introduce unified private header file
  amlogic: Move SCPI code to common directory
  amlogic: Move the SHA256 DMA driver to common directory
  amlogic: Move assembly helpers to common directory
  amlogic: Introduce directory parameters in the makefiles
  meson: Rename platform directory to amlogic
2019-09-12 10:58:43 +00:00
Soby Mathew 749b334694 Merge "mbedtls: use #include <...> instead of "..."" into integration 2019-09-11 16:21:29 +00:00
Justin Chadwell 1f4619796a Add UBSAN support and handlers
This patch adds support for the Undefined Behaviour sanitizer. There are
two types of support offered - minimalistic trapping support which
essentially immediately crashes on undefined behaviour and full support
with full debug messages.

The full support relies on ubsan.c which has been adapted from code used
by OPTEE.

Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-09-11 14:15:54 +01:00
Masahiro Yamada f906a44e9e libc: fix sparse warning for __assert()
Sparse warns this:

lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers

Add __dead2 to match the header declaration and C definition.

I also changed '__dead2 void' to 'void __dead2' for the consistency
with other parts.

Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-09-11 11:28:46 +09:00
Justin Chadwell 9dd94382bd Enable MTE support in both secure and non-secure worlds
This patch adds support for the new Memory Tagging Extension arriving in
ARMv8.5. MTE support is now enabled by default on systems that support
at EL0. To enable it at ELx for both the non-secure and the secure
world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving
and restoring when necessary in order to prevent register leakage
between the worlds.

Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-09-09 16:23:33 +01:00
Carlo Caione 01b2a7fc32 amlogic: Move the SHA256 DMA driver to common directory
The SHA256 DMA driver can be used by multiple SoCs. Move it to the
common directory.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
2019-09-05 10:39:30 +01:00
Carlo Caione 4a079c752b meson: Rename platform directory to amlogic
Meson is the internal code name for the SoC family. The correct name for
the platform should be Amlogic. Change the name of the platform
directory.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
2019-09-05 10:39:25 +01:00
Masahiro Yamada 948a0c0d3c mbedtls: use #include <...> instead of "..."
The #include "mbedtls/check_config.h" directive first searches for
the header in the relative path to mbedtls_config.h, i.e.
include/drivers/auth/mbedtls/mbedtls/check_config.h

Obviously, it does not exist since check_config.h is located in
the mbedtls project.

It is more sensible to use #include <...> form.

Change-Id: If72a71381f84e7748a2c9f07dd1176559d9bb1d2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-09-04 15:35:42 +09:00
Yann Gautier 2c2c9f1eb1 mmc: stm32_sdmmc2: manage max-frequency property from DT
If the max-frequency property is provided in the device tree mmc node,
it should be managed. The max allowed frequency will be the min between
this property value and what the card can support.

Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-02 17:53:14 +02:00
Yann Gautier 73680c230f stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.

The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.

An increase of BL2 size is also required when adding this new code.

Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2019-09-02 17:25:08 +02:00
Paul Beesley 30560911dd Merge "AArch64: Disable Secure Cycle Counter" into integration 2019-08-23 11:26:57 +00:00
Alexei Fedorov e290a8fcbc AArch64: Disable Secure Cycle Counter
This patch fixes an issue when secure world timing information
can be leaked because Secure Cycle Counter is not disabled.
For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD
bit on CPU cold/warm boot.
For the earlier architectures PMCR_EL0 register is saved/restored
on secure world entry/exit from/to Non-secure state, and cycle
counting gets disabled by setting PMCR_EL0.DP bit.
'include\aarch64\arch.h' header file was tided up and new
ARMv8.5-PMU related definitions were added.

Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-08-21 15:43:24 +01:00
Paul Beesley c3db45fb1d Merge "console: add a flag to prepend '\r' in the multi-console framework" into integration 2019-08-20 09:37:37 +00:00
Masahiro Yamada f51df47572 console: add a flag to prepend '\r' in the multi-console framework
Currently, console drivers prepend '\r' to '\n' by themselves. This is
common enough to be supported in the framework.

Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this
flag to ask the framework to transform LF into CRLF instead of doing
it by itself.

Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-08-19 17:00:08 +09:00
Alexei Fedorov ef430ff495 FVP_Base_AEMv8A platform: Fix cache maintenance operations
This patch fixes FVP_Base_AEMv8A model hang issue with
ARMv8.4+ with cache modelling enabled configuration.
Incorrect L1 cache flush operation to PoU, using CLIDR_EL1
LoUIS field, which is required by the architecture to be
zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced
with L1 to L2 and L2 to L3 (if L3 is present) cache flushes.
FVP_Base_AEMv8A model can be configured with L3 enabled by
setting `cluster0.l3cache-size` and `cluster1.l3cache-size`
to non-zero values, and presence of L3 is checked in
`aem_generic_core_pwr_dwn` function by reading
CLIDR_EL1.Ctype3 field value.

Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-08-16 11:30:37 +00:00
Alexei Fedorov 6c6a470fc1 AArch64: Align crash reporting output
This patch modifies crash reporting for AArch64 to provide
aligned output of register dump and GIC registers.

Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-08-15 14:23:27 +00:00
Julius Werner 402b3cf876 Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:45:03 -07:00
Julius Werner d5dfdeb65f Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:14:12 -07:00
Balint Dobszay 3d08461a2d Enable AMU for Cortex-Hercules
Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-31 15:04:03 +00:00
Soby Mathew 4129340717 Merge changes from topic "advk-serror" into integration
* changes:
  marvell/a3700: Prevent SError accessing PCIe link while it is down
  marvell: Switch to xlat_tables_v2
2019-07-26 09:26:14 +00:00
Soby Mathew 861264395f Merge changes from topic "gby/cryptocell-multi-vers" into integration
* changes:
  cryptocell: add product version awareness support
  cryptocell: move Cryptocell specific API into driver
2019-07-25 15:38:10 +00:00
Gilad Ben-Yossef 76f3c7dc8b cryptocell: add product version awareness support
Add support for multiple Cryptocell revisions which
use different APIs.

This commit only refactors the existing code in preperation to the addition
of another Cryptocell revisions later on.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I16d80b31afb6edd56dc645fee5ea619cc74f09b6
2019-07-25 13:38:07 +03:00
Gilad Ben-Yossef 36ec2bb0bc cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
  copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
  API and products.

Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
2019-07-25 13:29:15 +03:00
Soby Mathew f7fb88f668 Merge changes from topic "jts/spsr" into integration
* changes:
  Refactor SPSR initialisation code
  SSBS: init SPSR register with default SSBS value
2019-07-25 09:13:49 +00:00
Soby Mathew d38613df9a Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration
* changes:
  plat/mediatek/mt81*: Use new bl31_params_parse() helper
  plat/rockchip: Use new bl31_params_parse_helper()
  Add helper to parse BL31 parameters (both versions)
  Factor out cross-BL API into export headers suitable for 3rd party code
  Use explicit-width data types in AAPCS parameter structs
  plat/rockchip: Switch to use new common BL aux parameter library
  Introduce lightweight BL platform parameter library
2019-07-25 09:04:21 +00:00
John Tsichritzis c250cc3b1b SSBS: init SPSR register with default SSBS value
This patch introduces an additional precautionary step to further
enhance protection against variant 4. During the context initialisation
before we enter the various BL stages, the SPSR.SSBS bit is explicitly
set to zero. As such, speculative loads/stores are by default disabled
for all BL stages when they start executing. Subsequently, each BL
stage, can choose to enable speculative loads/stores or keep them
disabled.

This change doesn't affect the initial execution context of BL33 which
is totally platform dependent and, thus, it is intentionally left up to
each platform to initialise.

For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means
that, for Arm platforms, all BL stages start with speculative
loads/stores disabled.

Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-24 12:49:53 +01:00
Julius Werner d9af1f7b6f Add helper to parse BL31 parameters (both versions)
BL31 used to take a single bl31_params_t parameter structure with entry
point information in arg0. In commit 726002263 (Add new version of image
loading.) this API was changed to a more flexible linked list approach,
and the old parameter structure was copied into all platforms that still
used the old format. This duplicated code unnecessarily among all these
platforms.

This patch adds a helper function that platforms can optionally link to
outsource the task of interpreting arg0. Many platforms are just
interested in the BL32 and BL33 entry point information anyway. Since
some platforms still need to support the old version 1 parameters, the
helper will support both formats when ERROR_DEPRECATED == 0. This allows
those platforms to drop a bunch of boilerplate code and asynchronously
update their BL2 implementation to the newer format.

Change-Id: I9e6475adb1a7d4bccea666118bd1c54962e9fc38
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Julius Werner 57bf605772 Factor out cross-BL API into export headers suitable for 3rd party code
This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.

The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.

Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Julius Werner 9352be8803 Use explicit-width data types in AAPCS parameter structs
It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depends on the current execution environment. This would cause
problems if e.g. we used this structure to set up the entry point of an
AArch32 program from within an AArch64 program. (It doesn't seem like
any code is doing that today, but it's probably still a good idea to
write this defensively. Also, it helps with my next patch.)

Change-Id: I12c04a85611f2b6702589f3362bea3e6a7c9f776
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Soby Mathew 4dc74ca387 Merge "arm: Shorten the Firmware Update (FWU) process" into integration 2019-07-23 12:37:25 +00:00
Ambroise Vincent 37b70031e0 arm: Shorten the Firmware Update (FWU) process
The watchdog is configured with a default value of 256 seconds in order
to implement the Trusted Board Boot Requirements.

For the FVP and Juno platforms, the FWU process relies on a watchdog
reset. In order to automate the test of FWU, the length of this process
needs to be as short as possible. Instead of waiting for those 4 minutes
to have a reset by the watchdog, tell it to reset immediately.

There are no side effects as the value of the watchdog's load register
resets to 0xFFFFFFFF.

Tested on Juno.

Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-07-23 10:41:41 +01:00
Soby Mathew 53f3751b89 Merge "Cortex_hercules: Introduce preliminary cpu support" into integration 2019-07-23 09:33:15 +00:00
Soby Mathew 1d7dc63ca5 Merge "Enable MTE support unilaterally for Normal World" into integration 2019-07-23 08:55:10 +00:00
Julius Werner b852d229f3 Introduce lightweight BL platform parameter library
This patch adds some common helper code to support a lightweight
platform parameter passing framework between BLs that has already been
used on Rockchip platforms but is more widely useful to others as well.
It can be used as an implementation for the SoC firmware configuration
file mentioned in the docs, and is primarily intended for platforms
that only require a handful of values to be passed and want to get by
without a libfdt dependency. Parameters are stored in a linked list and
the parameter space is split in generic and vendor-specific parameter
types. Generic types will be handled by this code whereas
vendor-specific types have to be handled by a vendor-specific handler
function that gets passed in.

Change-Id: If3413d44e86b99d417294ce8d33eb2fc77a6183f
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-18 16:42:40 -07:00
Louis Mayencourt 294f9ef9f9 Cortex_hercules: Introduce preliminary cpu support
Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-07-16 16:36:51 +01:00
Remi Pommarel 6e9e15b0b2 marvell: Switch to xlat_tables_v2
Use v2 xlat tables library instead of v1 for marvell platforms.

Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Change-Id: I838a6a878a8353e84eea9529721761b478943f0a
2019-07-16 17:04:00 +02:00
Ambroise Vincent 52e91081a9 console: update skeleton
Update the skeleton implementation of the console interface.

The 32 bit version was outdated and has been copied from the 64 bit
version.

Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-07-16 13:01:02 +00:00
Soby Mathew d0d0f17164 Merge changes from topic "jc/shift-overflow" into integration
* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour
2019-07-16 10:11:27 +00:00
Sandrine Bailleux 70f7c4e121 Merge "AArch64: Add 128-bit integer types definitions" into integration 2019-07-12 08:37:24 +00:00
Soby Mathew b7e398d64c Enable MTE support unilaterally for Normal World
This patch enables MTE for Normal world if the CPU suppors it. Enabling
MTE for secure world will be done later.

Change-Id: I9ef64460beaba15e9a9c20ab02da4fb2208b6f7d
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-07-12 09:27:25 +01:00
Justin Chadwell 3e43121ed1 Update base code to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00
John Tsichritzis 274e8714ed Merge "Aarch64: Fix SCTLR bit definitions" into integration 2019-07-11 15:39:02 +00:00
Alexei Fedorov 394fa5d499 AArch64: Add 128-bit integer types definitions
This patch adds 128-bit integer types int128_t and uint128_t
for "__int128" and "unsigned __int128" supported by GCC and
Clang for AArch64.

Change-Id: I0e646d026a5c12a09fd2c71dc502082052256a94
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-07-10 12:22:58 +01:00
Alexei Fedorov c465515718 Aarch64: Fix SCTLR bit definitions
This patch removes incorrect SCTLR_V_BIT definition and adds
definitions for ARMv8.3-Pauth EnIB, EnDA and EnDB bits.

Change-Id: I1384c0a01f56f3d945833464a827036252c75c2e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-07-10 11:26:45 +01:00
Balint Dobszay f363deb6d4 Rename Cortex-Deimos to Cortex-A77
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-10 12:14:20 +02:00
Sandrine Bailleux bb2d778c74 Merge changes from topic "lw/n1_errata_fixes" into integration
* changes:
  Removing redundant ISB instructions
  Workaround for Neoverse N1 erratum 1275112
  Workaround for Neoverse N1 erratum 1262888
  Workaround for Neoverse N1 erratum 1262606
  Workaround for Neoverse N1 erratum 1257314
  Workaround for Neoverse N1 erratum 1220197
  Workaround for Neoverse N1 erratum 1207823
  Workaround for Neoverse N1 erratum 1165347
  Workaround for Neoverse N1 erratum 1130799
  Workaround for Neoverse N1 erratum 1073348
2019-07-04 06:58:51 +00:00