Commit Graph

1762 Commits

Author SHA1 Message Date
Marc Bonnici ce5b35c573 docs(maintainers): introduce SPMC maintainer section
Renamed the existing SPM entry to the SPMD and add myself
as the SPMC maintainer.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ic74659b119986df5fc229a4470049d289eeef21a
2022-05-11 09:53:40 +01:00
John Powell 5d796b3a25 fix(errata): workaround for Cortex-A78 erratum 2376745
Cortex-A78 erratum 2376745 is a cat B erratum that applies to revisions
r0p0 - r1p2 and is still open. The workaround is to set bit[0] of
CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and
not cause invalidation to other PE caches.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6f1a3a7d613c5ed182a7028f912e0f6ae3aa7f98
2022-05-09 19:09:22 +02:00
Marco Nelissen 3db9a39cb7 docs(maintainers): add new owners for Trusty SPD
Split TLK/Trusty SPD into two separate components and add additional
owners for Trusty SPD.

Signed-off-by: Marco Nelissen <marcone@google.com>
Change-Id: Ifabd1bb630fe4976e304fa29eac1c516ec6e2e18
2022-05-06 17:50:26 +02:00
Manish Pandey e8ad39759b Merge "feat(brbe): add BRBE support for NS world" into integration 2022-05-06 12:46:03 +02:00
Madhukar Pappireddy d82fae2680 Merge "docs(maintainers): update measured boot code owners" into integration 2022-05-05 22:27:35 +02:00
johpow01 744ad97445 feat(brbe): add BRBE support for NS world
This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disabled for all secure world, and cannot be used with ENABLE_RME.

This option is disabled by default, however, the FVP platform makefile
enables it for FVP builds.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I576a49d446a8a73286ea6417c16bd0b8de71fca0
2022-05-05 19:43:10 +02:00
Manish V Badarkhe 598d1fa85f docs(maintainers): add code owners for Firmware Update driver
Added myself and Sandrine Bailleux as code owners for Firmware
Update driver.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I34fad895c6236fedc814fb6da4b04fd7fbed9227
2022-05-04 16:43:40 +01:00
Manish Pandey b7bd9863dc Merge changes from topic "hm/make-refactor" into integration
* changes:
  docs(prerequisites): use LLVM utilities to build with clang
  build(make): use clang binutils to compile
2022-05-04 14:17:38 +02:00
Lauren Wehrmeister 1ced6cad52 Merge changes from topic "refactor-hw-config-load" into integration
* changes:
  docs(fvp): update loading addresses of HW_CONFIG
  docs(fconf): update device tree binding for FCONF
  feat(fvp): update HW_CONFIG DT loading mechanism
  refactor(st): update set_config_info function call
  refactor(fvp_r): update set_config_info function call
  refactor(arm): update set_config_info function call
  feat(fconf): add NS load address in configuration DTB nodes
2022-05-03 17:06:49 +02:00
Sandrine Bailleux 7cb76fdf1c docs(maintainers): update measured boot code owners
Propose myself as a code owner of the measured boot module.

Also do a couple of updates along the way:

 - Add the measured boot bindings document to the list of measured
   boot files.

 - Fix the list of FVP files. plat/arm/board/fvp/fvp_measured_boot.c
   does not exist anymore. It has been replaced by
   plat/arm/board/fvp/fvp_measured_{bl1,bl2,common}_boot.c files.

Change-Id: Ifb34f4f7c704b1db966b44428bbffd48c5e3c42b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-05-03 14:59:48 +02:00
Venkatesh Yadav Abbarapu be73459a94 feat(xilinx): add SPP/EMU platform support for versal
This patch adds SPP/EMU platform support for Xilinx Versal and
also updating the documentation.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ibdadec4d00cd33ea32332299e7a00de31dc9d60b
2022-05-02 22:49:24 +02:00
Madhukar Pappireddy 894c635b83 Merge changes I47014d72,Ibf00c386 into integration
* changes:
  docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS
  feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS
2022-04-29 23:12:21 +02:00
Jorge Ramirez-Ortiz ac4ac38c54
docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS
Document the RESET_TO_BL31 with parameters feature.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Change-Id: I47014d724f2eb822b69a112c3acee546fbfe82d5
2022-04-29 22:54:34 +02:00
Manish Pandey 145f665e07 Merge "docs(fvp): specify correct reference of the hw_config address" into integration 2022-04-29 13:52:59 +02:00
Harrison Mutai a5d36574fc docs(prerequisites): use LLVM utilities to build with clang
Makefile updated to use LLVM utilities instead of GNU utilities when
compiling with clang. `CROSS_COMPILE` is not required since this
dependency has been removed.

Change-Id: I19706b84b9310e07935516681b86596c04ef8ad6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-04-29 13:35:21 +02:00
Madhukar Pappireddy e34ea9b900 Merge "docs(build): update GCC to version 11.2-2022.02" into integration 2022-04-28 16:18:43 +02:00
Manish V Badarkhe b4a878367f docs(fvp): update loading addresses of HW_CONFIG
As per change [1], now HW_CONFIG gets loaded in secure and
non-secure memory. Hence updated the documentation to show
secure and non-secure load region of HW_CONFIG in FVP Arm
platform.

Additionally, added a note on how FW_CONFIG address gets
passed from BL2 to BL31/SP_MIN.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14620

Change-Id: I37e02ff4f433c87bccbe67c7df5ecde3017668b9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-04-28 07:09:53 +01:00
Manish V Badarkhe b80e751d99 docs(fconf): update device tree binding for FCONF
Added a description for the newly introduced 'ns-load-address' property
in the dtb-registry node of FCONF.

Change-Id: Ief8e8a55a6363fd42b23491d000b097b0c48453b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-04-28 07:09:53 +01:00
Madhukar Pappireddy 19a9cc3a1b Merge "docs(zynqmp): update the make command" into integration 2022-04-27 16:41:21 +02:00
Manish Pandey 9284d2129e Merge "refactor(twed): improve TWED enablement in EL-3" into integration 2022-04-27 11:01:52 +02:00
Venkatesh Yadav Abbarapu e8e7cdf3d6 docs(zynqmp): update the make command
Update the make command with the RESET_TO_BL31=1 addition.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I46cc81abb539773706348464b3061d20d94522e9
2022-04-27 08:42:27 +05:30
Manish V Badarkhe a0d3df66f3 docs(fvp): specify correct reference of the hw_config address
TB_FW_CONFIG DT no longer contains the address of HW_CONFIG; it has
been moved to the FW_CONFIG DT since the introduction of FCONF.
Hence updated the documentation accordingly.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I37b68502a89dbd521acd99f2cb3aeb0bd36a04e0
2022-04-26 12:02:43 +01:00
Joanna Farley e61c00fa4b Merge "docs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers" into integration 2022-04-26 12:18:18 +02:00
Sandrine Bailleux ab1c943981 Merge changes from topic "sb/mbedtls-2.28" into integration
* changes:
  docs(prerequisites): upgrade to mbed TLS 2.28.0
  build(deps): upgrade to mbed TLS 2.28.0
2022-04-26 07:49:06 +02:00
Sandrine Bailleux 5cae337337 docs(prerequisites): upgrade to mbed TLS 2.28.0
Upgrade to the latest and greatest 2.x release of Mbed TLS library
(i.e. v2.28.0) to take advantage of their bug fixes.

Note that the Mbed TLS project published version 3.x some time
ago. However, as this is a major release with API breakages, upgrading
to 3.x might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to mbed TLS 3.x after the v2.7
release of TF-A.

Change-Id: I887dfd87893169c7be53b986e6c43338d15949d7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-04-25 10:26:10 +02:00
Sandrine Bailleux 71a5543bcf docs(prerequisites): update Arm compilers download link
Right now, TF-A documentation recommends downloading Arm compilers
from:

  https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads

However, this page is now deprecated, as indicated by the banner at
the top of the page. When navigating to the new recommended page, one
can see the following note, which provides the rationale for the
deprecation:

  GNU Toolchain releases from Arm were published previously as two
  separate releases - one for A-profile and the other for R & M
  profiles (GNU Toolchain for A-profile processors and GNU Arm
  Embedded Toolchain).

  Arm GNU Toolchain releases unifies these two into a single release
  and the previous way of releases therefore have been
  discontinued. However, the previous releases will continue to be
  available for reference.

This patch updates the link to the new recommended place for compiler
downloads.

Change-Id: Iefdea3866a1af806a5db2d2288edbb63c543b8ee
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2022-04-25 08:19:44 +02:00
Sandrine Bailleux 94909893df Merge "docs: fix mailing lists URLs" into integration 2022-04-25 07:58:46 +02:00
Sieu Mun Tang 5ca81820de docs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers
Add Sieu Mun Tang and Benjamin Jit Loon Lim as new
Intel SocFPGA platform maintainers and remove the
rest of the Intel SocFPGA platform maintainers.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ieb9a35e278d70a12351aaccab90ddc7be09dc861
2022-04-23 09:50:35 +08:00
Olivier Deprez 65b13bace4 Merge changes from topic "ffa_el3_spmc" into integration
* changes:
  feat(spmc): add support for direct req/resp
  feat(spmc): add support for handling FFA_ERROR ABI
  feat(spmc): add support for FFA_MSG_WAIT
  feat(spmc): add function to determine the return path from the SPMC
  feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
  feat(spmd): update SPMC init flow to use EL3 implementation
  feat(spmc): add FF-A secure partition manager core
  feat(spmc): prevent read only xlat tables with the EL3 SPMC
  feat(spmc): enable building of the SPMC at EL3
  refactor(spm_mm): reorganize secure partition manager code
2022-04-22 21:09:13 +02:00
Sandrine Bailleux f4a55e6b32 docs: fix mailing lists URLs
With the transition to mailman3, the URLs of TF-A and TF-A Tests
mailing lists have changed. However, we still refer to the old
location, which are now dead links.

Update all relevant links throughout the documentation.

There is one link referring to a specific thread on the TF-A mailing
list in the SPM documentation, for which I had to make a guess as to
what's the equivalent mailman3 URL. The old URL scheme indicates that
the thread dates from February 2020 but beyond that, I could not make
sense of the thread id within the old URL so I picked the most likely
match amongst the 3 emails posted on the subject in this time period.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Reported-by: Kuohong Wang <kuohong.wang@mediatek.com>
Change-Id: I83f4843afd1dd46f885df225931d8458152dbb58
2022-04-21 10:26:23 +02:00
Jayanth Dodderi Chidanand 781d07a421 refactor(twed): improve TWED enablement in EL-3
The current implementation uses plat_arm API under generic code.
"plat_arm" API is a convention used with Arm common platform layer
and is reserved for that purpose. In addition, the function has a
weak definition which is not encouraged in TF-A.

Henceforth, removing the weak API with a configurable macro "TWED_DELAY"
of numeric data type in generic code and simplifying the implementation.
By default "TWED_DELAY" is defined to zero, and the delay value need to
be explicitly set by the platforms during buildtime.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I25cd6f628e863dc40415ced3a82d0662fdf2d75a
2022-04-17 23:48:10 +01:00
Marc Bonnici 1d63ae4d0d feat(spmc): enable building of the SPMC at EL3
Introduce build flag for enabling the secure partition
manager core, SPMC_AT_EL3. When enabled, the SPMC module
will be included into the BL31 image. By default the
flag is disabled.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5ea1b953e5880a07ffc91c4dea876a375850cf2a
2022-04-13 09:44:49 +01:00
Daniel Boulby a58a25e5d2 docs(build): update GCC to version 11.2-2022.02
This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com.

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: Ia14de2c7d9034a6f0bc56535e961fffc81bcbf29
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-04-12 10:22:30 +01:00
Bipin Ravi 63446c27d1 fix(errata): workaround for Cortex-X2 erratum 2147715
Cortex-X2 erratum 2147715 is a Cat B erratum that applies to revision
r2p0 and is fixed in r2p1. The workaround is to set CPUACTLR_EL1[22]=1,
which will cause the CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I2d81867486d9130f2c36cd4554ca9a8f37254b57
2022-04-11 17:00:19 -05:00
Jayanth Dodderi Chidanand d9e984cc30 docs(build): update the feature enablement flags
Adding the newly introduced build flags for feature enablement of the
following features:
1.FEAT_AMUv1p1 - ENABLE_FEAT_AMUv1p1
2.FEAT_CSV2_2  - ENABLE_FEAT_CSV2_2
3.FEAT_VHE     - ENABLE_FEAT_VHE
4.FEAT_DIT     - ENABLE_FEAT_DIT
5.FEAT_SB      - ENABLE_FEAT_SB
6.FEAT_SEL2    - ENABLE_FEAT_SEL2

Also as part of feature detection mechanism, we now support three
states for each of these features, allowing the flags to take either
(0 , 1 , 2) values. Henceforth the existing feature build options are
converted from boolean to numeric type and is updated accordingly
in this patch.

The build flags take a default value and will be internally enabled
when they become mandatory from a particular architecture version
and upwards. Platforms have the flexibility to overide this
internal enablement via this feature specific explicit build flags.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I0090c8c780c2e7d1a50ed9676983fe1df7a35e50
2022-04-05 17:34:17 +01:00
Joanna Farley 0263c968a7 Merge changes Ic1796898,I93bd392a into integration
* changes:
  fix(errata): workaround for Cortex A78 AE erratum 2395408
  fix(errata): workaround for Cortex A78 AE erratum 2376748
2022-03-29 00:21:37 +02:00
Soby Mathew ad88c37080 Merge changes from topic "rme-attest" into integration
* changes:
  feat(rme): add dummy realm attestation key to RMMD
  feat(rme): add dummy platform token to RMMD
2022-03-28 18:32:27 +02:00
Joanna Farley 2ea18c7df3 Merge changes from topics "ls1088a", "ls1088a-prepare" into integration
* changes:
  docs(layerscape): add ls1088a soc and board support
  feat(ls1088aqds): add ls1088aqds board support
  feat(ls1088ardb): add ls1088ardb board support
  feat(ls1088a): add new SoC platform ls1088a
  build(changelog): add new scopes for ls1088a
  feat(bl2): add support to separate no-loadable sections
  refactor(layerscape): refine comparison of inerconnection
  feat(layerscape): add soc helper macro definition for chassis 3
  feat(nxp-gic): add some macros definition for gicv3
  feat(layerscape): add CHASSIS 3 support for tbbr
  feat(layerscape): define more chassis 3 hardware address
  feat(nxp-crypto): add chassis 3 support
  feat(nxp-dcfg): add Chassis 3 support
  feat(lx2): enable DDR erratas for lx2 platforms
  feat(layerscape): print DDR errata information
  feat(nxp-ddr): add workaround for errata A050958
  feat(layerscape): add new soc errata a010539 support
  feat(layerscape): add new soc errata a009660 support
  feat(nxp-ddr): add rawcard 1F support
  fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
  fix(nxp-tools): fix create_pbl print log
  build(changelog): add new scopes for NXP driver
2022-03-28 17:40:59 +02:00
Soby Mathew a0435105f2 feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
parameters:
    * Fid (0xC400001B2).
    * Attestation key buffer PA (the realm attestation key is copied
      at this address by the monitor).
    * Attestation key buffer length as input and size of realm
      attesation key as output.
    * Type of elliptic curve.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I12d8d98fd221f4638ef225c9383374ddf6e65eac
2022-03-28 15:02:01 +02:00
Rex-BC Chen 933bf32c14 docs(maintainers): add the new maintainer for MediaTek SoCs
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia9409127e91e55726db0856e3f13f009d3c7c866
2022-03-28 17:49:31 +08:00
Jiafei Pan 6e4e294a07 docs(layerscape): add ls1088a soc and board support
Update document for nxp-layerscape to add ls1088a SoC and ls1088ardb,
update maintainer of ls1088a platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ic7fdc7b1bbf22e50646991093366a88ee523ffe3
2022-03-27 23:24:24 +08:00
Jiafei Pan 96a8ed14b7 feat(bl2): add support to separate no-loadable sections
Add new options SEPARATE_BL2_NOLOAD_REGION to separate no-loadable
sections (.bss, stack, page tables) to a ram region specified
by BL2_NOLOAD_START and BL2_NOLOAD_LIMIT.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I844ee0fc405474af0aff978d292c826fbe0a82fd
2022-03-27 23:24:24 +08:00
Soby Mathew 0f9159b7eb feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
    * Fid (0xC40001B3).
    * Platform token PA (the platform token is copied at this address by
      the monitor). The challenge object needs to be passed by
      the caller in this buffer.
    * Platform token len.
    * Challenge object len.

When calling the SMC, the platform token buffer received by EL3 contains
the challenge object. It is not used on the FVP and is only printed to
the log.

Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I8b2f1d54426c04e76d7a3baa6b0fbc40b0116348
2022-03-25 17:12:26 +00:00
Varun Wadekar 3f4d81dfd2 fix(errata): workaround for Cortex A78 AE erratum 2395408
Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum states, "A translation table walk that matches an
existing L1 prefetch with a read request outstanding on CHI might
fold into the prefetch, which might lead to data corruption for
a future instruction fetch"

This erratum is avoided by setting CPUACTLR2_EL1[40] to 1 to
disable folding of demand requests into older prefetches with
L2 miss requests outstanding.

SDEN is available at https://developer.arm.com/documentation/SDEN-1707912

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic17968987ca3c67fa7f64211bcde6dfcb35ed5d6
2022-03-24 10:55:48 +00:00
Varun Wadekar 92e870843e fix(errata): workaround for Cortex A78 AE erratum 2376748
Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

The erratum states, "A PE executing a PLDW or PRFM PST instruction
that lies on a mispredicted branch path might cause a second PE
executing a store exclusive to the same cache line address to fail
continuously."

The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.

SDEN is available at https://developer.arm.com/documentation/SDEN-1707912

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d
2022-03-24 10:53:17 +00:00
Joanna Farley e638c228b8 Merge "build(sptool): handle uuid field in SP layout file" into integration 2022-03-23 14:31:31 +01:00
Manish Pandey 2ff6a49ea6 Merge changes from topic "stm32mp13" into integration
* changes:
  feat(stm32mp1): select platform compilation either by flag or DT
  feat(stm32mp1-fdts): add support for STM32MP13 DK board
  feat(stm32mp1-fdts): add DDR support for STM32MP13
  feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
  feat(stm32mp1): updates for STM32MP13 device tree compilation
  feat(stm32mp1-fdts): add DT files for STM32MP13
  feat(dt-bindings): add TZC400 bindings for STM32MP13
  feat(stm32mp1): add "Boot mode" management for STM32MP13
  feat(stm32mp1): manage HSLV on STM32MP13
  feat(stm32mp1): add sdmmc compatible in platform define
  feat(st-sdmmc2): allow compatible to be defined in platform code
  feat(stm32mp1): update IO compensation on STM32MP13
  feat(stm32mp1): call pmic_voltages_init() in platform init
  feat(st-pmic): add pmic_voltages_init() function
  feat(stm32mp1): update CFG0 OTP for STM32MP13
  feat(stm32mp1): usb descriptor update for STM32MP13
  feat(st-clock): add clock driver for STM32MP13
  feat(dt-bindings): add bindings for STM32MP13
  feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
  feat(stm32mp1): use only one filter for TZC400 on STM32MP13
  feat(stm32mp1): add a second fixed regulator
  feat(stm32mp1): adaptations for STM32MP13 image header
  feat(stm32mp1): update boot API for header v2.0
  feat(stm32mp1): update IP addresses for STM32MP13
  feat(stm32mp1): add part numbers for STM32MP13
  feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
  feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
  feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
  feat(stm32mp1): remove unsupported features on STM32MP13
  feat(stm32mp1): update memory mapping for STM32MP13
  feat(stm32mp1): introduce new flag for STM32MP13
  feat(st): update stm32image tool for header v2
2022-03-22 16:42:16 +01:00
Sebastien Pasdeloup bdec516ee8 feat(stm32mp1): introduce new flag for STM32MP13
STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can be used as monitor.
STM32MP13 uses the header v2.0 format for stm32image generation
for BL2.

Change-Id: Ie5b0e3230c5e064fe96f3561fc5b3208914dea53
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-03-21 10:53:55 +01:00
Pali Rohár 19a2d5188b docs(a3k): update documentation about DEBUG mode for UART
DEBUG mode can be enabled without any issue for Armada 37xx and also for
other A7K/A8K/CN913x. There is no incompatibility with Xmodem protocol
like it was written before, because Armada 37xx UART images do not print
anything on UART during image transfer and A7K/A8K/CN913x BLE image
automatically turn off debugging output when booting over UART. Looks
like this incorrect information is some relict from the past.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I85adc3c21036656b4620c4692e04330cad11ea2f
2022-03-16 12:38:43 +01:00
Bipin Ravi 1fe4a9d181 fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
2022-03-10 23:57:14 -06:00