Richard Gong 1ae7b6f6b1 intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB ... Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c		2020-10-24 11:00:42 +08:00
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aarch64	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
drivers	plat: intel: Fix CCU initialization for Agilex	2020-06-08 22:03:48 +00:00
include	intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB	2020-10-24 11:00:42 +08:00
soc	intel: common: Remove urgent from mailbox async	2020-10-24 11:00:42 +08:00
bl2_plat_mem_params_desc.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00
socfpga_delay_timer.c	plat: intel: Additional instruction required to enable global timer	2020-06-08 22:03:54 +00:00
socfpga_image_load.c	intel: Implement platform specific system reset 2	2019-12-30 10:17:04 +08:00
socfpga_psci.c	intel: Fix argument type for mailbox driver	2020-02-25 16:41:47 +08:00
socfpga_sip_svc.c	intel: common: Remove urgent from mailbox async	2020-10-24 11:00:42 +08:00
socfpga_storage.c	intel: Refactor common platform code [2/5]	2019-11-28 12:47:58 +08:00
socfpga_topology.c	intel: Platform common code refactor	2019-08-01 16:39:27 +08:00