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arm-trusted-firmware/plat/nvidia/tegra/soc/t194/platform_t194.mk

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Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
#
Tegra194: remove unused platform configs This patch cleans the makefile to remove unused platform config options. Change-Id: I96d9795c0f0ba593de96017dc9a401d7c2ab471a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-11-29 23:34:58 +00:00
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
#
# SPDX-License-Identifier: BSD-3-Clause
#
# platform configs
Tegra: introduce plat_enable_console() This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-08-21 22:01:31 +01:00
ENABLE_CONSOLE_SPE := 0
$(eval $(call add_define,ENABLE_CONSOLE_SPE))
Tegra194: config to enable/disable strict checking mode This patch adds a new configuration option to the platform makefiles that disables/enables strict checking mode. The config is enabled by default. Change-Id: I727dd0facee88d9517bf6956eaf9163eba25c8bb Signed-off-by: Steven Kao <skao@nvidia.com>
2017-12-12 22:39:15 +00:00
ENABLE_STRICT_CHECKING_MODE := 1
$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
RESET_TO_BL31 := 1
PROGRAMMABLE_RESET_ADDRESS := 1
COLD_BOOT_SINGLE_CPU := 1
# platform settings
TZDRAM_BASE := 0x40000000
$(eval $(call add_define,TZDRAM_BASE))
Tegra194: core and cluster count values This patch updates the total number of CPU clusters and number of cores per cluster, in the platform makefile. Change-Id: I569ebc1bb794ecab09a1043511b3d936bf450428 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-08-23 22:59:09 +01:00
PLATFORM_CLUSTER_COUNT := 4
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
Tegra194: core and cluster count values This patch updates the total number of CPU clusters and number of cores per cluster, in the platform makefile. Change-Id: I569ebc1bb794ecab09a1043511b3d936bf450428 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-08-23 22:59:09 +01:00
PLATFORM_MAX_CPUS_PER_CLUSTER := 2
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
Tegra194: program stream ids for XUSB T194 XUSB has support for XUSB virtualization. It will have one physical function (PF) and four Virtual function (VF) There were below two SIDs for XUSB until T186. 1) #define TEGRA_SID_XUSB_HOST 0x1bU 2) #define TEGRA_SID_XUSB_DEV 0x1cU We have below four new SIDs added for VF(s) 3) #define TEGRA_SID_XUSB_VF0 0x5dU 4) #define TEGRA_SID_XUSB_VF1 0x5eU 5) #define TEGRA_SID_XUSB_VF2 0x5fU 6) #define TEGRA_SID_XUSB_VF3 0x60U When virtualization is enabled then we have to disable SID override and program above SIDs in below newly added SID registers in XUSB PADCTL MMIO space. These registers are TZ protected and so need to be done in ATF. a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) This change disables SID override and programs XUSB SIDs in above registers to support both virtualization and non-virtualization. Change-Id: I38213a72999e933c44c5392441f91034d3b47a39 Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
2017-08-01 23:53:04 +01:00
MAX_XLAT_TABLES := 25
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
$(eval $(call add_define,MAX_XLAT_TABLES))
Tegra194: increase MAX_MMAP_REGIONS macro value This patch increases the MAX_MMAP_REGIONS value to 30 from 25 to allow addition of more MMU mappings. Change-Id: I5c758c432f5cc77299608e25ba2fd92c3822379d Signed-off-by: Steven Kao <skao@nvidia.com>
2017-09-29 09:32:34 +01:00
MAX_MMAP_REGIONS := 30
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
Tegra: introduce plat_enable_console() This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-08-21 22:01:31 +01:00
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
Tegra194: console driver compilation from platform makefiles This patch includes the console driver from individual platform makefile, to allow future platforms to include consoles of their choice. Change-Id: I4c92199717da410c8b5e8d45af67f4345f743dbd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-11-15 23:52:01 +00:00
lib/cpus/aarch64/denver.S \
Tegra194: toggle SE clock during context save/restore This patch adds support to toggle SE clock, using the bpmp_ipc interface, to enable SE context save/restore. The SE sequence mostly gets called during System Suspend/Resume. Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7 Signed-off-by: steven kao <skao@nvidia.com>
2018-01-03 03:09:04 +00:00
${COMMON_DIR}/drivers/bpmp_ipc/intf.c \
${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
${COMMON_DIR}/drivers/smmu/smmu.c \
${SOC_DIR}/drivers/mce/mce.c \
Tegra194: Enable MCE driver This patch enable MCE driver for T19x SoC. The MCE driver takes care of the communication with the MCE firmware to achieve: - Cold boot - Warm boot - Core/Cluster/System Power management - Custom MCE requests Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d Signed-off-by: Steven Kao <skao@nvidia.com>
2017-01-05 09:04:40 +00:00
${SOC_DIR}/drivers/mce/nvg.c \
${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Tegra194: drivers: SE and RNG1/PKA1 context save support This patch adds the driver, to implement the programming sequence to save/restore hardware context, during System Suspend/Resume. Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9 Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Jeff Tsai <jefft@nvidia.com>
2017-06-23 09:18:58 +01:00
${SOC_DIR}/drivers/se/se.c \
Tegra194: platform support for memctrl/smmu drivers This patch adds platform support for the Memory Controller and SMMU drivers, for the Tegra194 SoC. Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-31 19:41:00 +01:00
${SOC_DIR}/plat_memctrl.c \
Tegra194: base commit for the platform This patch creates the base commit for the Tegra194 platform, from Tegra186 code base. Change-Id: I1c77e4984f7ff39655f3fb79633d13d533707ede Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2018-04-10 01:48:58 +01:00
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c \
Tegra194: platform support for memctrl/smmu drivers This patch adds platform support for the Memory Controller and SMMU drivers, for the Tegra194 SoC. Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-31 19:41:00 +01:00
${SOC_DIR}/plat_sip_calls.c \
Tegra194: cleanup references to Tegra186 This patch cleans up all references to the Tegra186 family of SoCs. Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-11-10 19:04:42 +00:00
${SOC_DIR}/plat_smmu.c \
${SOC_DIR}/plat_trampoline.S
Tegra: introduce plat_enable_console() This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2019-08-21 22:01:31 +01:00
ifeq (${ENABLE_CONSOLE_SPE},1)
BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S
endif