2015-08-25 12:33:14 +01:00
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/*
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2015-12-29 02:12:59 +00:00
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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2015-08-25 12:33:14 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TEGRA_DEF_H__
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#define __TEGRA_DEF_H__
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2016-12-12 22:24:17 +00:00
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/*******************************************************************************
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* MCE apertures used by the ARI interface
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*
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* Aperture 0 - Cpu0 (ARM Cortex A-57)
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* Aperture 1 - Cpu1 (ARM Cortex A-57)
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* Aperture 2 - Cpu2 (ARM Cortex A-57)
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* Aperture 3 - Cpu3 (ARM Cortex A-57)
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* Aperture 4 - Cpu4 (Denver15)
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* Aperture 5 - Cpu5 (Denver15)
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******************************************************************************/
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#define MCE_ARI_APERTURE_0_OFFSET 0x0
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#define MCE_ARI_APERTURE_1_OFFSET 0x10000
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#define MCE_ARI_APERTURE_2_OFFSET 0x20000
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#define MCE_ARI_APERTURE_3_OFFSET 0x30000
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#define MCE_ARI_APERTURE_4_OFFSET 0x40000
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#define MCE_ARI_APERTURE_5_OFFSET 0x50000
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#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
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/* number of apertures */
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#define MCE_ARI_APERTURES_MAX 6
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/* each ARI aperture is 64KB */
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#define MCE_ARI_APERTURE_SIZE 0x10000
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/*******************************************************************************
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* CPU core id macros for the MCE_ONLINE_CORE ARI
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******************************************************************************/
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#define MCE_CORE_ID_MAX 8
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#define MCE_CORE_ID_MASK 0x7
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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2016-01-19 03:03:19 +00:00
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* These values are used by the PSCI implementation during the `CPU_SUSPEND`
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* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
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* parameter.
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2015-08-25 12:33:14 +01:00
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******************************************************************************/
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2016-01-19 03:03:19 +00:00
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#define PSTATE_ID_CORE_IDLE 6
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#define PSTATE_ID_CORE_POWERDN 7
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#define PSTATE_ID_SOC_POWERDN 2
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 8
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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2015-12-29 02:12:59 +00:00
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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#define TEGRA186_TOP_WDT_IRQ 49
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#define TEGRA186_AON_WDT_IRQ 50
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#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Tegra Miscellanous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE 0x00100000
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2016-02-17 23:07:49 +00:00
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#define HARDWARE_REVISION_OFFSET 0x4
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2016-04-02 23:41:20 +01:00
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2016-03-03 21:52:52 +00:00
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#define MISCREG_PFCFG 0x200C
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2015-08-25 12:33:14 +01:00
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2016-03-12 01:18:51 +00:00
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/*******************************************************************************
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* Tegra TSA Controller constants
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******************************************************************************/
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#define TEGRA_TSA_BASE 0x02400000
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2016-12-15 19:54:51 +00:00
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/*******************************************************************************
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* TSA configuration registers
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******************************************************************************/
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#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010
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#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038
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#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010
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#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008
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#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008
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#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100
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#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018
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#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018
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#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028
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#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018
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#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008
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#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018
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#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028
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#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038
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#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008
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#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
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#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018
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#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
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#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_STREAMID_BASE 0x02C00000
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#define TEGRA_MC_BASE 0x02C10000
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2016-12-13 00:14:57 +00:00
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
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#define MC_TZRAM_BASE_LO 0x2194
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#define TZRAM_BASE_LO_SHIFT 12
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#define TZRAM_BASE_LO_MASK 0xFFFFF
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#define MC_TZRAM_BASE_HI 0x2198
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#define TZRAM_BASE_HI_SHIFT 0
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#define TZRAM_BASE_HI_MASK 3
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#define MC_TZRAM_SIZE 0x219C
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#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
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#define MC_TZRAM_CARVEOUT_CFG 0x2190
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#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
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#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
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#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
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#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Tegra UART Controller constants
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******************************************************************************/
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#define TEGRA_UARTA_BASE 0x03100000
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#define TEGRA_UARTB_BASE 0x03110000
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#define TEGRA_UARTC_BASE 0x0C280000
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#define TEGRA_UARTD_BASE 0x03130000
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#define TEGRA_UARTE_BASE 0x03140000
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#define TEGRA_UARTF_BASE 0x03150000
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#define TEGRA_UARTG_BASE 0x0C290000
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2016-05-18 21:39:16 +01:00
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/*******************************************************************************
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* Tegra Fuse Controller related constants
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******************************************************************************/
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#define TEGRA_FUSE_BASE 0x03820000
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#define OPT_SUBREVISION 0x248
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#define SUBREVISION_MASK 0xFF
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* GICv2 & interrupt handling related constants
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******************************************************************************/
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#define TEGRA_GICD_BASE 0x03881000
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#define TEGRA_GICC_BASE 0x03882000
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2016-03-03 21:52:52 +00:00
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/*******************************************************************************
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* Security Engine related constants
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******************************************************************************/
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#define TEGRA_SE0_BASE 0x03AC0000
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#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
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#define TEGRA_PKA1_BASE 0x03AD0000
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#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
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#define TEGRA_RNG1_BASE 0x03AE0000
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#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE 0x05000000
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x0C2E0000
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2016-12-23 08:05:13 +00:00
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#define TEGRA_TMRUS_SIZE 0x1000
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE 0x0C360000
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/*******************************************************************************
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* Tegra scratch registers constants
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******************************************************************************/
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#define TEGRA_SCRATCH_BASE 0x0C390000
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2016-12-13 00:46:44 +00:00
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#define SECURE_SCRATCH_RSV1_LO 0x658
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#define SECURE_SCRATCH_RSV1_HI 0x65C
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2016-03-03 21:52:52 +00:00
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#define SECURE_SCRATCH_RSV6 0x680
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#define SECURE_SCRATCH_RSV11_LO 0x6A8
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#define SECURE_SCRATCH_RSV11_HI 0x6AC
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2016-05-23 19:47:34 +01:00
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#define SECURE_SCRATCH_RSV53_LO 0x7F8
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#define SECURE_SCRATCH_RSV53_HI 0x7FC
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2016-07-29 13:10:59 +01:00
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#define SECURE_SCRATCH_RSV54_HI 0x804
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#define SECURE_SCRATCH_RSV55_LO 0x808
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#define SECURE_SCRATCH_RSV55_HI 0x80C
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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2016-09-23 22:28:16 +01:00
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* Tegra Memory Mapped Control Register Access constants
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2015-08-25 12:33:14 +01:00
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******************************************************************************/
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#define TEGRA_MMCRAB_BASE 0x0E000000
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2016-09-23 22:28:16 +01:00
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/*******************************************************************************
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* Tegra Memory Mapped Activity Monitor Register Access constants
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******************************************************************************/
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#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000
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#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000
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2015-08-25 12:33:14 +01:00
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/*******************************************************************************
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* Tegra SMMU Controller constants
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******************************************************************************/
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2017-01-24 08:19:46 +00:00
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#define TEGRA_SMMU0_BASE 0x12000000
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2015-08-25 12:33:14 +01:00
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2015-12-30 23:15:08 +00:00
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE 0x30000000
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2016-05-26 00:35:04 +01:00
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#define TEGRA_TZRAM_SIZE 0x40000
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2015-12-30 23:15:08 +00:00
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2015-08-25 12:33:14 +01:00
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#endif /* __TEGRA_DEF_H__ */
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