Commit Graph

91 Commits

Author SHA1 Message Date
Christoph Müllner 826ba363c4 rockchip: Add support for the stack protector
It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signed-off-by: Christoph Müllner <christophm30@gmail.com>
2020-12-01 11:54:57 +01:00
Thomas Hebb e7b586987c rockchip: don't crash if we get an FDT we can't parse
When we parse the param from BL2, we try to parse it as a FDT and then,
if that fails, as aux params. However, we don't sufficiently distinguish
between failure modes in the first step: specifically, if we are given
an FDT with good magic that we can't parse for some other reason (e.g.
not enough space in our buffer), we still attempt to parse it as aux
params even though that's guaranteed to fatal. Instead, we should either
fail with a more descriptive message or continue to boot without parsing
the FDT.

This patch takes the latter approach, since all we currently get from
the FDT is non-critical UART params.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: I1e98f1fcda4f78e6b45e86956288bafe58b113e4
2020-07-04 15:37:25 -07:00
Hugh Cole-Baker 8109f738ff rockchip: increase FDT buffer size
The size of buffer currently used to store the FDT passed from U-Boot as
a platform parameter is not large enough to store some RK3399 device
trees. The largest RK3399 device tree currently in U-Boot (for the
Pinebook Pro) is about 70KB in size when passed to TF-A, so increase the
buffer size to 128K which gives some headroom for possibly larger FDTs
in future.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Change-Id: I414caf20683cd47c02ee470dfa988544f3809919
2020-06-08 23:03:42 +01:00
Andre Przywara 98964f0523 16550: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-02-25 09:34:38 +00:00
XiaoDong Huang 11a0a46a89 rockchip: fix definition of struct param_ddr_usage
In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage need to be adjust to "DDR_REGION_NR_MAX + 1".

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifc09da2c8f8afa1aebcc78f8fbc21ac95abdece2
2020-02-17 08:53:39 +08:00
Louis Mayencourt f1be00da0b Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-01-28 11:10:48 +00:00
Vasily Khoruzhick d52331d01e plat/rockchip: initialize reset and poweroff GPIOs with known invalid value
And return NULL if we didn't get them in bl aux params otherwise reset and poweroff
will be broken on platforms that do not have reset and poweroff GPIOs.

Fixes: c1185ffde1 ("plat/rockchip: Switch to use new common BL aux parameter library")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Change-Id: Ic6cf6383d8f05d745e2c5d5e1b1df38514ea8429
2019-11-17 12:38:24 -08:00
Paul Beesley 99becbe3df Merge changes from topic "rockchip-uart-fixes" into integration
* changes:
  rockchip: rk3399: store actual debug uart information on suspend
  rockchip: move dt-coreboot uart distinction into param handling code
  rockchip: make uart baudrate configurable
  rockchip: px30: add uart5 as option for serial output
2019-08-15 15:30:13 +00:00
Heiko Stuebner dd4a0d1618 rockchip: move dt-coreboot uart distinction into param handling code
Rockchip platforms can be booted from either u-boot or coreboot.

So far the Coreboot-console was initizalized from a coreboot data struct
in the early_param2 callbacks and dt-based consoles with data from the
rockchip_get_uart_* functions.

But later code may also need this console information for example for
special suspend handling. To make this easy follow a suggestion from
Julius Werner and move the coreboot<->dt distinction into the
rockchip_get_uart_* functions, thus making correct data about the used
uart available to all Rockchip platform code at all times.

This includes a new rockchip_get_uart_clock as well, because while the
dt-platforms right now always just default the rate defined in a constant
Coreboot provides its own field for the clock rate and we don't want to
loose that information for the console init. Similarly the rk_uart_*
variables should move into the non-Coreboot code, to prevent them from
being marked as unused, which also requires the rk_get_uart_* functions
to move below the actual dt-parsing.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac
2019-08-09 09:40:19 +02:00
Heiko Stuebner 30970e0f29 rockchip: make uart baudrate configurable
A previous patch already allowed to configure the uart output from the
devicetree, but on Rockchip platforms we also have the issue of different
vendors using different baudrates for their uarts.

For example, rk3399 has a default baudrate of 115200 which is true for
ChromeOS-devices and boards from Theobroma-Systems, while all the boards
using the vendor boot chain actually use a baudrate of 1500000.

Similarly the newly added px30 has a default of said 1500000 but some
boards may want to use the more widely used 115200.

The devicetree stdout-path node already contains the desired baudrate,
so add simple code to parse it from there and override the default,
which stays unchanged.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I7412139c3df3073a1996eb508ec08642ec6af90d
2019-08-05 17:52:06 +02:00
Heiko Stuebner 5f441a7b3d rockchip: px30: add uart5 as option for serial output
The px30 mini-evb can use either uart2 (muxed with the sd-card pins) or
uart5 via its pin header for serial output. Uart5 is especially useful
when needing to boot from the sd-card, where uart2 obviously is not
useable.

So add the uart5 constants and it as uart option for the serial-param
handler.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ib88df7a55d761ee104d312c9953a13de3beba1c4
2019-08-05 09:45:09 +02:00
Julius Werner 402b3cf876 Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:45:03 -07:00
Julius Werner d5dfdeb65f Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:14:12 -07:00
Soby Mathew d38613df9a Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration
* changes:
  plat/mediatek/mt81*: Use new bl31_params_parse() helper
  plat/rockchip: Use new bl31_params_parse_helper()
  Add helper to parse BL31 parameters (both versions)
  Factor out cross-BL API into export headers suitable for 3rd party code
  Use explicit-width data types in AAPCS parameter structs
  plat/rockchip: Switch to use new common BL aux parameter library
  Introduce lightweight BL platform parameter library
2019-07-25 09:04:21 +00:00
Julius Werner 3e02c7436c plat/rockchip: Use new bl31_params_parse_helper()
The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementations on this platform to transparently switch over to the
version 2 parameter structure.

Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-24 11:04:03 -07:00
Julius Werner 57bf605772 Factor out cross-BL API into export headers suitable for 3rd party code
This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.

The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.

Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:34 -07:00
Julius Werner c1185ffde1 plat/rockchip: Switch to use new common BL aux parameter library
This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly split in
generic and vendor-specific parameters and the COREBOOT_TABLE
parameter is now generic, the parameter type number for that parameter
has to change. Since it only affects coreboot which always builds TF as
a submodule and includes its headers directly to get these constants,
this should not cause any issues. In general, after this point, we
should avoid changing already assigned parameter type numbers whenever
possible.

Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-23 20:25:30 -07:00
XiaoDong Huang 010d6ae338 rockchip: px30: support px30
px30 is a Quad-core soc and Cortex-a53 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system

Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2019-07-09 17:07:13 +08:00
Heiko Stuebner 3e6945e919 rockchip: drop rockchip-specific imported linker symbols for bl31
In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the general
code also imports them as BL_CODE_BASE and BL_CODE_END.

So we can just use the general symbols and can drop the duplication.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d
2019-05-29 12:06:30 +02:00
Christoph Müllner 220c33a2c5 rockchip: Allow console device to be set by DTB.
Currently the compile-time constant PLAT_RK_UART_BASE defines
which UART is used as console device. E.g. on RK3399 it is set
to UART2. That means, that a single bl31 image can not be used
for two boards, which just differ on the UART console.

This patch addresses this limitation by parsing the "stdout-path"
property from the "chosen" node in the DTB. The expected property
string is expected to have the form "serialN:XXX", with
N being either 0, 1, 2, 3 or 4. When the property is found, it will
be used to override PLAT_RK_UART_BASE.

Tested on RK3399-Q7, with a stdout-path of "serial0:115200n8".

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: Iafe1320e77ab006c121f8d52745d54cef68a48c7
2019-05-01 17:52:53 +02:00
Heiko Stuebner 4200e5aae7 rockchip: only include libfdt in non-coreboot cases
While mainline u-boot always expects to submit the devicetree
as platform param, coreboot always uses the existing parameter
structure. As libfdt is somewhat big, it makes sense to limit
its inclusion to where necessary and thus only to non-coreboot
builds.

libfdt itself will get build in all cases, but only the non-
coreboot build will actually reference and thus include it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I4c5bc28405a14e6070917e48a526bfe77bab2fb7
2019-04-26 23:36:17 +02:00
Heiko Stuebner 82e18f8998 rockchip: add common aarch32 support
There are a number or ARMv7 Rockchip SoCs that are very similar in their
bringup routines to the existing arm64 SoCs, so there is quite a high
commonality possible here.

Things like virtualization also need psci and hyp-mode and instead of
trying to cram this into bootloaders like u-boot, barebox or coreboot
(all used in the field), re-use the existing infrastructure in TF-A
for this (both Rockchip plat support and armv7 support in general).

So add core support for aarch32 Rockchip SoCs, with actual soc support
following in a separate patch.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b
2019-04-25 13:37:56 +02:00
Heiko Stuebner 3b5b888d1b rockchip: Allow socs with undefined wfe check bits
Some older socs like the rk3288 do not have the necessary registers
to check the wfi/wfe state of the cpu cores. Allow this case an "just"
do an additional delay similar to how the Linux kernel handles smp
right now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I0f67af388b06b8bfb4a9bac411b4900ac266a77a
2019-04-25 13:37:56 +02:00
Heiko Stuebner c3aaabaf7e rockchip: move pmusram assembler code to a aarch64 subdir
The current code doing power-management from sram is highly
arm64-specific so should live in a corresponding subdirectory
and not in the common area.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9
2019-04-25 13:37:56 +02:00
Heiko Stuebner 7029e80683 rockchip: add an fdt parsing stub for platform param
The Rockchip ATF platform can be entered from both Coreboot and U-Boot.
While Coreboot does submit the list of linked parameter structs as
platform param, upstream u-boot actually always provides a pointer
to a devicetree as parameter.
This results in current ATF not running at all when started from U-Boot.

To fix this, add a stub that checks if the parameter is a fdt so we
can at least boot and not get stuck. Later on we can extend this with
actual parsing of information from the devicetree.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-14 22:45:15 +01:00
Antonio Nino Diaz d31dcdc5f6 rockchip: Fix GICv2 interrupts
After the removal of deprecated interfaces in TF 2.0 the migration to
the new GIC driver interfaces was done incorrectly in rk3328 and rk3368:
2d6f1f01b1 ("rockchip: Migrate to new interfaces").

In the GICv2 driver it is mandated that all interrupts are Group 0
interrupts. This patch simply moves all Group 1 interrupts to Group 0.

Change-Id: I224c0135603eb5b81bd512976361500c0d129a91
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-28 14:35:50 +00:00
Antonio Nino Diaz 09d40e0e08 Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-04 10:43:17 +00:00
Antonio Nino Diaz c3cf06f1a3 Standardise header guards across codebase
All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-08 10:20:19 +00:00
John Tsichritzis a623832683 Replace S-EL3 references by EL3
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is
meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix
has been removed from wherever it was used as "S-EL3".

Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-10-10 12:11:32 +01:00
Antonio Nino Diaz 2d6f1f01b1 rockchip: Migrate to new interfaces
- Migrate to new GIC interfaces.
- Migrate to bl31_early_platform_setup2().
- Use bl31_warm_entrypoint() instead of psci_entrypoint().
- Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE.
- Update Makefile paths.
- Remove references to removed build options.
- Use private definition of bl31_params_t.

Change-Id: I860341594b5c868b2fcaa59d23957ee718472ef1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-28 15:34:17 +01:00
Daniel Boulby 5eddd22e05 rockchip: Add plat_is_my_cpu_primary function
This function is required for platforms where
COLD_BOOT_SINGLE_CPU=0 however it was missing from rockchip
platforms

Change-Id: I32a85f226a4f22085a27113903f34bdb6f28dbcc
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-08-15 13:39:33 +01:00
Roberto Vargas b2805dabaa Remove .func and .endfunc assembler directives
These directives are only used when stabs debugging information
is used, but we use ELF which uses DWARF debugging information.
Clang assembler doesn't support these directives, and removing
them makes the code more compatible with clang.

Change-Id: I2803f22ebd24c0fe248e04ef1b17de9cec5f89c4
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-07-11 09:22:56 +01:00
Roberto Vargas 033648652f Make TF UUID RFC 4122 compliant
RFC4122 defines that fields are stored in network order (big endian),
but TF-A stores them in machine order (little endian by default in TF-A).
We cannot change the future UUIDs that are already generated, but we can store
all the bytes using arrays and modify fiptool to generate the UUIDs with
the correct byte order.

Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-06-14 14:41:00 +01:00
Masahiro Yamada 0a2d5b43c8 types: use int-ll64 for both aarch32 and aarch64
Since commit 031dbb1224 ("AArch32: Add essential Arch helpers"),
it is difficult to use consistent format strings for printf() family
between aarch32 and aarch64.

For example, uint64_t is defined as 'unsigned long long' for aarch32
and as 'unsigned long' for aarch64.  Likewise, uintptr_t is defined
as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64.

A problem typically arises when you use printf() in common code.

One solution could be, to cast the arguments to a type long enough
for both architectures.  For example, if 'val' is uint64_t type,
like this:

  printf("val = %llx\n", (unsigned long long)val);

Or, somebody may suggest to use a macro provided by <inttypes.h>,
like this:

  printf("val = %" PRIx64 "\n", val);

But, both would make the code ugly.

The solution adopted in Linux kernel is to use the same typedefs for
all architectures.  The fixed integer types in the kernel-space have
been unified into int-ll64, like follows:

    typedef signed char           int8_t;
    typedef unsigned char         uint8_t;

    typedef signed short          int16_t;
    typedef unsigned short        uint16_t;

    typedef signed int            int32_t;
    typedef unsigned int          uint32_t;

    typedef signed long long      int64_t;
    typedef unsigned long long    uint64_t;

[ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ]

This gets along with the codebase shared between 32 bit and 64 bit,
with the data model called ILP32, LP64, respectively.

The width for primitive types is defined as follows:

                   ILP32           LP64
    int            32              32
    long           32              64
    long long      64              64
    pointer        32              64

'long long' is 64 bit for both, so it is used for defining uint64_t.
'long' has the same width as pointer, so for uintptr_t.

We still need an ifdef conditional for (s)size_t.

All 64 bit architectures use "unsigned long" size_t, and most 32 bit
architectures use "unsigned int" size_t.  H8/300, S/390 are known as
exceptions; they use "unsigned long" size_t despite their architecture
is 32 bit.

One idea for simplification might be to define size_t as 'unsigned long'
across architectures, then forbid the use of "%z" string format.
However, this would cause a distortion between size_t and sizeof()
operator.  We have unknowledge about the native type of sizeof(), so
we need a guess of it anyway.  I want the following formula to always
return 1:

  __builtin_types_compatible_p(size_t, typeof(sizeof(int)))

Fortunately, ARM is probably a majority case.  As far as I know, all
32 bit ARM compilers use "unsigned int" size_t.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-27 18:35:02 +09:00
Masahiro Yamada 57d1e5faf2 Fix pointer type mismatch of handlers
Commit 4c0d039076 ("Rework type usage in Trusted Firmware") changed
the type usage in struct declarations, but did not touch the definition
side.  Fix the type mismatch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-27 18:35:02 +09:00
Dimitris Papastamos 6ab136c258
Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statements
Fix switch statements to comply with MISRA rules
2018-03-29 13:20:05 +01:00
Joel Hutton 9f85f9e379 Clean usage of void pointers to access symbols
Void pointers have been used to access linker symbols, by declaring an
extern pointer, then taking the address of it. This limits symbols
values to aligned pointer values. To remove this restriction an
IMPORT_SYM macro has been introduced, which declares it as a char
pointer and casts it to the required type.

Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2018-03-27 13:20:27 +01:00
Jonathan Wright 649c48f5dc plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.

Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
2018-03-26 12:43:05 +01:00
davidcunado-arm 334e1ceb48
Merge pull request #1236 from dbasehore/gic-save-restore
RK3399 GIC save/restore
2018-02-01 08:58:23 +00:00
Derek Basehore 3284ce15ba rockchip: Disable rdist before pwr_dm_suspend is called
This disables the redistributor before either of the pwr_dm_suspend
functions are called. This is because the rdist save code in the
rk3399 rockchip_soc_sys_pwr_dm_suspend function requires that each
redistributor be disabled before saving state.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2018-01-25 22:09:23 -08:00
Julius Werner 890abc33e4 rockchip: Move to MULTI_CONSOLE_API
This patch changes all Rockchip platforms to use the new
MULTI_CONSOLE_API. The platform-specific plat_crash_console
implementations are removed so that the platform can use the ones from
the common platform code instead.

Also change the registers used in plat_crash_print_regs. The existing
use of x16 and x17 has always been illegal, since those registers are
reserved for use by the linker as a temporary scratch registers in
intra-procedure-call veneers and can never be expected to maintain their
values across a function call.

Change-Id: I8249424150be8d5543ed4af93b56756795a5288f
Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19 15:21:12 -08:00
Julius Werner 3c250b9ab6 rockchip: Use coreboot-supplied serial console on coreboot systems
This patch changes all Rockchip platforms to initialize the serial
console with information supplied by coreboot rather than hardcoded
base address and divisor values if BL31 is run on top of coreboot.
Moving the BL2-to-BL31 parameter parsing as early as possible to ensure
that the console is available for all following code.

Also update the Rockchip platform to use MULTI_CONSOLE_API.

Change-Id: I670d350fa2f8b8133539f91ac14977ab47db60d9
Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19 15:21:12 -08:00
Julius Werner a33e763c40 rockchip: Implement a panic handler that will reboot the system
The current Rockchip platform code retains the "common" default panic
handler which simply hangs the system (until the watchdog kicks in, if
enabled). This is usually not a great user experience.

This patch implements a Rockchip-specific panic handler that calls the
platform's reboot implementation to reset the system.

Change-Id: I4cbe09c48f1b3f86ebdfc0108c186565f9ffc119
Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-12-12 15:00:34 -08:00
Lin Huang 2adcad64dc rockchip/rk3399: save and restore pd_alive register
pd_alive control cru, grf, timer, gpio and wdt, when
turn off logic power rail, these register value will
back to reset value, we need to save them value in suspend
and restore them when resuem, since timer will reinitial
in kernel, so it not need to save/restore.

Change-Id: I0fc2a011d3cdc04b66ffbf728e769eb28b51ee38
Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-08-29 15:00:40 +08:00
Lin Huang 9aadf25c22 rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.

Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-08-29 11:53:29 +08:00
Julius Werner 64726e6d61 Add new alignment parameter to func assembler macro
Assembler programmers are used to being able to define functions with a
specific aligment with a pattern like this:

    .align X
  myfunction:

However, this pattern is subtly broken when instead of a direct label
like 'myfunction:', you use the 'func myfunction' macro that's standard
in Trusted Firmware. Since the func macro declares a new section for the
function, the .align directive written above it actually applies to the
*previous* section in the assembly file, and the function it was
supposed to apply to is linked with default alignment.

An extreme case can be seen in Rockchip's plat_helpers.S which contains
this code:

  [...]
  endfunc plat_crash_console_putc

  .align 16
  func platform_cpu_warmboot
  [...]

This assembles into the following plat_helpers.o:

  Sections:
  Idx Name                             Size  [...]  Algn
   9 .text.plat_crash_console_putc 00010000  [...]  2**16
  10 .text.platform_cpu_warmboot   00000080  [...]  2**3

As can be seen, the *previous* function actually got the alignment
constraint, and it is also 64KB big even though it contains only two
instructions, because the .align directive at the end of its section
forces the assembler to insert a giant sled of NOPs. The function we
actually wanted to align has the default constraint. This code only
works at all because the linker just happens to put the two functions
right behind each other when linking the final image, and since the end
of plat_crash_console_putc is aligned the start of platform_cpu_warmboot
will also be. But it still wastes almost 64KB of image space
unnecessarily, and it will break under certain circumstances (e.g. if
the plat_crash_console_putc function becomes unused and its section gets
garbage-collected out).

There's no real way to fix this with the existing func macro. Code like

 func myfunc
 .align X

happens to do the right thing, but is still not really correct code
(because the function label is inserted before the .align directive, so
the assembler is technically allowed to insert padding at the beginning
of the function which would then get executed as instructions if the
function was called). Therefore, this patch adds a new parameter with a
default value to the func macro that allows overriding its alignment.

Also fix up all existing instances of this dangerous antipattern.

Change-Id: I5696a07e2fde896f21e0e83644c95b7b6ac79a10
Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-08-15 16:37:08 -07:00
Isla Mitchell ee1ebbd18e Fix order of remaining platform #includes
This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.

Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-07-14 10:50:41 +01:00
Varun Wadekar fb7d32e588 Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.

NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14 15:00:13 -07:00
Lin Huang 84597b57f9 rockchip: check wakeup cpu when resume
unlike rk3399 and rk3368, there are some rockchip 64bit SOC
do not have CPUPD, and pmu_cpuson_entrypoint() is common
function for rockchip platform, so we need to check wakeup
cpu when resume.

Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff
Signed-off-by: Lin Huang <hl@rock-chips.com>
2017-06-08 10:01:19 +08:00
Lin Huang 4e836d3578 rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.

Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-08 09:59:53 +08:00