Commit Graph

7793 Commits

Author SHA1 Message Date
Nina Wu f85f37d4f7 Initialize platform for MediaTek mt8192
- Add basic platform setup
- Add mt8192 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address

Change-Id: Ife34622105404a8227441aab939e3c55c96374e9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-07-31 10:46:22 +08:00
Madhukar Pappireddy 499f192c1d Merge "fconf: spm: minor bug fix" into integration 2020-07-30 23:57:25 +00:00
Andre Przywara fa30f73b37 arm_fpga: Support uploading a custom command line
The command line for BL33 payloads is typically taken from the DTB. On
"normal" systems the bootloader will put the right version in there, but
we typically don't use one on the FPGAs.
To avoid editing (and possibly re-packaging) the DTB for every change in
the command line, try to read it from some "magic" memory location
instead. It can be easily placed there by the tool that uploads the
other payloads to the FPGA's memory. BL31 will then replace the existing
command line in the DTB with that new string.

To avoid reading garbage, check the memory location for containing a
magic value. This is conveniently chosen to be a simple ASCII string, so
it can just preceed the actual command line in a text file:
--------------------------------
CMD:console=ttyAMA0,38400n8 debug loglevel=8
--------------------------------

Change-Id: I5923a80332c9fac3b4afd1a6aaa321233d0f60da
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-07-30 17:18:37 +01:00
Olivier Deprez db1ef41a78 SPM: build OP-TEE as an S-EL1 Secure Partition
Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.

Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
2020-07-30 15:56:13 +00:00
Manish V Badarkhe 582e4e7b28 Makefile, doc: Make OPENSSL_DIR variable as build option for tools
Openssl directory path is hardcoded to '/usr' in the makefile
of certificate generation and firmware encryption tool using
'OPENSSL_DIR' variable.

Hence changes are done to make 'OPENSSL_DIR' variable as
a build option so that user can provide openssl directory
path while building the certificate generation and firmware
encryption tool.

Also, updated the document for this newly created build option

Change-Id: Ib1538370d2c59263417f5db3746d1087ee1c1339
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-30 15:00:48 +01:00
Manish Pandey f0b1864f8e Merge "fdts: n1sdp: DTS file for single-chip and multi-chip environment." into integration 2020-07-30 13:41:16 +00:00
Grzegorz Jaszczyk 3045dfe10c docs: marvell: update PHY porting layer description
The purpose of rx_training had changed after last update. Currently it
is not supposed to help with providing static parameters for porting
layer. Instead, it aims to suit the parameters per connection.

Change-Id: I2a146b71e2e20bd264c090a9a627d0b6bc56e052
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-07-30 15:15:53 +02:00
Grzegorz Jaszczyk 663f6bcfe8 docs: marvell: update path in marvell documentation
Change-Id: I0cebbaa900aa518700f13cbf02f8a97e0c76b21c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-07-30 15:15:52 +02:00
Konstantin Porotchkin eed02440af docs: marvell: update build instructions with CN913x
Add references to the OcteonTX2 CN913x family.

Change-Id: I172a8e3d061086bf4843acad014c113c80359e01
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2020-07-30 15:15:52 +02:00
Grzegorz Jaszczyk 2c9d263682 plat: marvell: octeontx: add support for t9130
CN-9130 has single CP0 inside the package and 2 additional one from MoChi
interface. In case of db-9130-modular board the MCI interface is routed to:
- on-board CP115 (MCI0)
- extension board CP115 (MCI1)

The board is based on DIMM DDR.

The 9130 has up to 3CP, and decoding windows looks like below:

  (free for further use)
 .----------. 0xf800 0000
 | CP2 CFG  |
 '----------' 0xf600 0000
 | CP1 CFG  |
 '----------' 0xf400 0000
 | CP0 CFG  |
 '----------' 0xf200 0000
 | AP CFG   |
 '----------' 0xf000 0000
  (free for further use)
 .----------. 0xec00 0000
 | SPI      |
 | MEM_MAP  | (Currently not opened)
 '----------' 0xe800 0000
 | PEX2_CP2 |
 '----------' 0xe700 0000
 | PEX1_CP2 |
 '----------' 0xe600 0000
 | PEX0-CP2 |
 '----------'
 .----------. 0xe500 0000
 | PEX2_CP1 |
 '----------' 0xe400 0000
 | PEX1_CP1 |
 '----------' 0xe300 0000
 | PEX0-CP1 |
 '----------'
 .----------. 0xe200 0000
 | PEX2-CP0 |
 '----------' 0xe100 0000
 | PEX1-CP0 |
 '----------' 0xe000 0000
 | PEX0-CP0 |
 | 512MB    |
 '----------' 0xc000 0000

Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-07-30 15:15:52 +02:00
Alex Evraev 12c66c6b48 plat: marvell: t9130: add SVC support
As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.

Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3
Signed-off-by: Alex Evraev <alexev@marvell.com>
2020-07-30 15:15:52 +02:00
Grzegorz Jaszczyk 885cd821f8 plat: marvell: t9130: update AVS settings
Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.

Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-07-30 15:15:52 +02:00
Ben Peled 5bc3643e57 plat: marvell: t9130: pass actual CP count for load_image
Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.

Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9
Signed-off-by: Ben Peled <bpeled@marvell.com>
2020-07-30 15:15:52 +02:00
Alex Evraev ebf307bfef plat: marvell: armada: a7k: add support to SVC validation mode
Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz

Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2
Signed-off-by: Alex Evraev <alexev@marvell.com>
2020-07-30 15:15:52 +02:00
Moti Buskila 4827068989 plat: marvell: armada: add support for twin-die combined memory device
the twin-die combined memory device should be treated as
X8 device and not as X16 one. This patch is required to
re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade.

Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97
Signed-off-by: Moti Buskila <motib@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2020-07-30 15:15:40 +02:00
Andre Przywara 000653b467 fdts: n1sdp: DTS file for single-chip and multi-chip environment.
N1SDP supports both single-chip and multi-chip environment.
Added  DTS file for both type of environment.
Enabled DTS files compilation for N1SDP platform.

Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0
Co-authored-by: Robin Murphy <Robin.Murphy@arm.com>
Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com>
Co-authored-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
2020-07-30 18:44:54 +05:30
Manish Pandey bef0192a2e fconf: spm: minor bug fix
This patch fixes a bug where wrong panic was caused when the number
of SP was same as max limit.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9ace62d8d5bcdc410eeacdd9d33d55a7be5fcc8e
2020-07-30 13:07:30 +01:00
Mark Dykes 4db3a8870a Merge "GIC-600: Fix MISRA-2012 defects" into integration 2020-07-29 19:24:53 +00:00
Alexei Fedorov b29c350cda GIC-600: Fix MISRA-2012 defects
This patch fixes violation of Rules 10.1, 10.4,
11.9 and 13.2 reported by MISRA-2012 scan.

Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-29 16:51:05 +00:00
Madhukar Pappireddy f3be7e2855 Merge "docs/fvp: update SGI and RD FVP list" into integration 2020-07-29 15:20:03 +00:00
Alexei Fedorov 77a386907a Aarch32 xlat_tables lib: Fix MISRA-2012 defects
This patch fixes violation of Rules 2.1, 7.3, 10.1,
10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by
MISRA-2012 scan and adds braces for conditional
statements according to the TF-A coding style.

Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-29 12:48:34 +00:00
joanna.farley 833abc61a4 Merge "doc: secure partition manager design" into integration 2020-07-29 10:34:09 +00:00
Madhukar Pappireddy 439dcf50c5 Merge "Fix broken link in documentation" into integration 2020-07-29 00:07:42 +00:00
Madhukar Pappireddy 6346dfce79 Merge "plat/nvidia: tegra: Enable SMCCC_ARCH_SOC_ID feature" into integration 2020-07-28 18:31:59 +00:00
Madhukar Pappireddy 25a7612682 Merge "plat/arm: Disable SMCCC_ARCH_SOC_ID feature" into integration 2020-07-28 18:31:52 +00:00
Madhukar Pappireddy a6151e7c85 Merge "SMCCC: Introduce function to check SMCCC function availability" into integration 2020-07-28 18:31:47 +00:00
johpow01 526f2bddd5 Fix broken link in documentation
The link to the exception handling framework page on the System Design /
Firmware Design / Section 4.3 just links to itself, so I changed it to
link to the exception handling framework component document.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1
2020-07-28 13:07:25 -05:00
Sandrine Bailleux 894eb3eefa Merge "doc: use docker to build documentation" into integration 2020-07-28 15:08:47 +00:00
Mark Dykes ffef797d89 Merge "TZ DMC620 driver: Fix MISRA-2012 defects" into integration 2020-07-27 21:30:29 +00:00
Alexei Fedorov 858e69e85e TZ DMC620 driver: Fix MISRA-2012 defects
This patch fixes defects 10.3, 10.4, 10.7, 20.7
reported by MISRA-2012 scan and adds braces for
conditional statements according to the TF-A
coding style.

Change-Id: If84ed31cdd55bc8e7cdd2a5f48c0dacc25792112
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-27 15:04:14 +01:00
Manish V Badarkhe 0a2126a572 plat/nvidia: tegra: Enable SMCCC_ARCH_SOC_ID feature
Enabled 'SMCCC_ARCH_SOC_ID' feature for Nvidia Tegra platforms.

Change-Id: If17415f42304c6518aeead8dfe5909c378aaa777
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-26 08:16:42 +01:00
Manish V Badarkhe c7bacd40d8 plat/arm: Disable SMCCC_ARCH_SOC_ID feature
Currently, soc-revision information is not available for arm
platforms hence disabled 'SMCCC_ARCH_SOC_ID' feature for all arm
platforms.

Change-Id: I1ab878c6a4c8fecfff63bc6dde83e3ecefe20279
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-26 08:16:42 +01:00
Manish V Badarkhe 6f0a2f04ab SMCCC: Introduce function to check SMCCC function availability
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally
returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to
be not correct for the platform which doesn't implement soc-id
functionality i.e. functions to retrieve both soc-version and
soc-revision.
Hence introduced a platform function which will check whether SMCCC
feature is available for the platform.

Also, updated porting guide for the newly added platform function.

Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-26 08:16:29 +01:00
Madhukar Pappireddy f5d9d89593 Merge "plat/arm: spm: add support for RESET_TO_BL31" into integration 2020-07-24 19:59:56 +00:00
Manish Pandey cc9cb29ae7 plat/arm: spm: add support for RESET_TO_BL31
SPM(BL32) and hafnium(BL33) expect their manifest base address in x0
register, which is updated during BL2 stage by parsing fw_config.
In case of RESET_TO_BL31 it has to be updated while populating
entry point information.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I6f4a97f3405029bd6ba25f0935e2d1f74bb95517
2020-07-24 16:46:48 +01:00
André Przywara 1dd157964a Merge "arm_fpga: Add support for topology self-discovery" into integration 2020-07-24 14:45:11 +00:00
Javier Almansa Sobrino 727bbf680d arm_fpga: Add support for topology self-discovery
As secondary cores show up, they populate an array to
announce themselves so plat_core_pos_by_mpidr() can
return an invalid COREID code for any non-existing
MPIDR that it is queried about.

The Power Domain Tree Description is populated with
a topology based on the maximum harcoded values.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
2020-07-24 15:06:42 +01:00
Lauren Wehrmeister 1056ddce76 Merge "Revert workaround for Neoverse N1 erratum 1800710" into integration 2020-07-23 20:02:15 +00:00
johpow01 f0bbaebc7e Revert workaround for Neoverse N1 erratum 1800710
This reverts commit 11af40b630, reversing
changes made to 2afcf1d4b8.

This errata workaround did not work as intended so we are reverting this
change.  In the future, when the corrected workaround is published in an
SDEN, we will push a new workaround.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I20aa064c1bac9671939e657bec269d32b9e75a97
2020-07-23 13:05:45 -05:00
Alexei Fedorov e6e7d71285 TF-A Aarch32: optimise memcpy4()
This patch makes optimisation of Aarch32 memcpy4()
function.

Change-Id: If9cdaa4a1224f88fb14df8a308a645344b6c4f1c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-07-23 18:35:49 +01:00
Madhukar Pappireddy e0887b71f8 Merge "plat: imx: common: implement IMX_SIP_AARCH32" into integration 2020-07-23 14:04:41 +00:00
Manish Pandey 710b313cb7 Merge changes from topic "tf-cleanup" into integration
* changes:
  plat/arm: Move fconf population after the enablement of MMU
  lib/fconf: Update 'set_fw_config_info' function
  lib/fconf: Update data type of config max size
  plat/arm: Check the need for firmware update only once
  plat/arm: sgm: Use consistent name for tb fw config node
2020-07-23 13:16:34 +00:00
Manish V Badarkhe a07c101a4d plat/arm: Move fconf population after the enablement of MMU
In BL2, fw_config's population happened before the cache gets
enabled.
Hence to boost the performance, moved fw_config's population
after cache gets enabled (i.e. after MMU gets enabled).

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2e75cabd76b1cb7a660f6b72f409ab40d2877284
2020-07-23 02:11:22 +00:00
Manish V Badarkhe f441718936 lib/fconf: Update 'set_fw_config_info' function
Updated the function 'set_fw_config_info' to make it generic
by doing below changes:

1. Rename function name from 'set_fw_config_info' to 'set_config_info'
2. Take image_id as an argument so that this function can set any
   config information.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Icf29e19d3e9996d8154d84dbbbc76712fab0f0c1
2020-07-23 02:11:13 +00:00
Manish V Badarkhe a4ff9d7e1e lib/fconf: Update data type of config max size
Update the data type of the member 'config_max_size' present in the
structure 'dyn_cfg_dtb_info_t' to uint32_t.

This change is being done so that dyn_cfg_dtb_info_t and image_info
structure should use same data type for maximum size.

Change-Id: I9b5927a47eb8351bbf3664b8b1e047ae1ae5a260
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-23 02:11:05 +00:00
Manish V Badarkhe a249a9d9e7 plat/arm: Check the need for firmware update only once
Currently, the need for firmware update is being checked twice
in the code hence modifications are done to do this check only
once and set the global variable.
Then this global variable helps to decide whether to go for
normal boot or firmware update flow.

Change-Id: I8469284555a8039786f34670f9dc4830f87aecc1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-23 02:10:57 +00:00
Manish V Badarkhe d958f37d50 plat/arm: sgm: Use consistent name for tb fw config node
Renamed node for trusted boot fw config from 'plat_arm_bl2' to
'tb_fw-config'.

Change-Id: I2e16b6f4d272292ec1855daafd014e851436dd9b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-23 02:10:48 +00:00
Vijayenthiran Subramaniam e09559fd7d docs/fvp: update SGI and RD FVP list
Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and
add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual
Platforms.

Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2020-07-22 22:24:47 +05:30
joanna.farley 3ee148d643 Merge changes from topics "af/add_measured_boot_bl1_bl2", "af/add_measured_boot_driver", "af/add_measured_boot_driver_support", "af/add_measured_boot_fconf", "af/add_measured_boot_fvp" into integration
* changes:
  plat/arm/board/fvp: Add support for Measured Boot
  TF-A: Add support for Measured Boot driver to FCONF
  TF-A: Add support for Measured Boot driver in BL1 and BL2
  TF-A: Add Event Log for Measured Boot
  TF-A: Add support for Measured Boot driver
2020-07-22 16:35:11 +00:00
Manish Pandey 43f7d88799 Merge changes from topic "stm32-scmi" into integration
* changes:
  stm32mp1: SCMI clock and reset service in SP_MIN
  dts: bindings: stm32mp1: define SCMI clock and reset domain IDs
2020-07-22 12:15:02 +00:00