Commit Graph

10379 Commits

Author SHA1 Message Date
Sayanta Pattanayak 70d986ddbb feat(spmc): prevent read only xlat tables with the EL3 SPMC
If using the EL3 SPMC ensure that we don't mark the translation
tables as read only. The SPMC requires the ability to map and
unmap a partitions RX/TX buffers at runtime.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ibb78a6a2e3847ce4ec74ce81a9bb61ce34fec24c
2022-04-13 09:44:52 +01:00
Marc Bonnici 1d63ae4d0d feat(spmc): enable building of the SPMC at EL3
Introduce build flag for enabling the secure partition
manager core, SPMC_AT_EL3. When enabled, the SPMC module
will be included into the BL31 image. By default the
flag is disabled.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5ea1b953e5880a07ffc91c4dea876a375850cf2a
2022-04-13 09:44:49 +01:00
Marc Bonnici b61d94a1a2 refactor(spm_mm): reorganize secure partition manager code
In preparation for adding the EL3 SPMC configuration as defined in
the FF-A specification, restructure the existing SPM_MM code.

With this restructuring of the code, the 'spm_mm' directory is
renamed as 'spm' and the code inside has been split into two
sub-directories named 'common' and 'spm_mm'. The code in 'spm_mm'
directory contains the code that implements the MM interface.
In subsequent patches, the 'spmc' directory will be introduced
under the 'spm' directory providing the code that implements
the 'FF-A' interface.

Currently the common functionality for S-EL1 partitions is
limited to assembler functions to enter and exit an SP
synchronously.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I37739b9b53bc68e151ab5c1c0c6a15b3ee362241
2022-04-08 15:36:22 +01:00
Manish Pandey 9bd3cb5c96 Merge changes I573e6478,I52dc3bee,I7e543664 into integration
* changes:
  feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
  feat(gic600ae_fmu): disable SMID for unavailable blocks
  feat(gic600ae_fmu): introduce support for RAS error handling
2022-04-08 14:42:45 +02:00
Manish Pandey 141791088e Merge "build(changelog): add new scope for TI platform" into integration 2022-04-07 17:44:31 +02:00
Varun Wadekar 6a1c17c770 feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
The following SMIDs are disabled by default.

* GICD: MBIST REQ error and GICD FMU ClkGate override
* PPI: MBIST REQ error and PPI FMU ClkGate override
* ITS: MBIST REQ error and ITS FMU ClkGate override

This patch explicitly enables them during the FMU init sequence.

Change-Id: I573e64786e3318d4cbcd07d0a1caf25f8e6e9200
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2022-04-07 15:21:40 +02:00
Manish Pandey f6ca81ddfb Merge changes from topic "jc/detect_feat" into integration
* changes:
  docs(build): update the feature enablement flags
  refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags
  refactor(el3-runtime): add arch-features detection mechanism
2022-04-07 15:19:04 +02:00
Manish Pandey fe029b5829 Merge changes from topic "mapping" into integration
* changes:
  feat(debug): update print_memory_map.py
  feat(bl_common): add XLAT tables symbols in linker script
2022-04-07 14:55:58 +02:00
Yann Gautier d16bfe0fef feat(debug): update print_memory_map.py
Add some entries in blx_symbols, that are used when the flag
SEPARATE_CODE_AND_RODATA is not enabled (__RO_* and __TEXT_RESIDENT_*).
Add all new symbols that were not yet present in the script.
Correct __BSS_END to __BSS_END__, and add __BSS_START__.
Add new *_XLAT_TABLE_* symbols.
As those strings are longer than 22, update display format string to
be dependent on the longest string.
The script also skips lines for which the _START__ and _END__
symbols have the same address (empty sections).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I6c510ced6116b35d14ee2cb7a6711405604380d6
2022-04-07 13:46:31 +02:00
Varun Wadekar 3f0094c15d feat(gic600ae_fmu): disable SMID for unavailable blocks
This patch updates the gic600_fmu_init function to disable all safety
mechanisms for a block ID that is not present on the platform. All
safety mechanisms for GIC-600AE are enabled by default and should be
disabled for blocks that are not present on the platform to avoid
false positive RAS errors.

Change-Id: I52dc3bee9a8b49fd2e51d7ed851fdc803a48e6e3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2022-04-07 10:00:23 +02:00
Yann Gautier bb5b942e6f feat(bl_common): add XLAT tables symbols in linker script
Add __BASE_XLAT_TABLE_START__/_END__ and __XLAT_TABLE_START__/_END__
symbols in the linker script to have them in the .map file.
This allows displaying those areas when running memory map script.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I768a459c5cecc403a9b81b36a71397ecc3179f4f
2022-04-06 18:07:36 +02:00
Varun Wadekar 308dce4067 feat(gic600ae_fmu): introduce support for RAS error handling
The GIC-600AE uses a range of RAS features for all RAMs, which include
SECDED, ECC, and Scrub, software and bus error reporting. The GIC makes
all necessary information available to software through Armv8.2 RAS
architecture compliant register space.

This patch introduces support to probe the FMU_ERRGSR register to find
the right error record. Once the correct record is identified, the
"handler" function queries the FMU_ERR<m>STATUS register to further
identify the block ID, safety mechanism and the architecturally defined
primary error code. The description of the error is displayed on the
console to simplify debug.

Change-Id: I7e543664b74457afee2da250549f4c3d9beb1a03
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2022-04-06 08:14:39 +01:00
Jayanth Dodderi Chidanand d9e984cc30 docs(build): update the feature enablement flags
Adding the newly introduced build flags for feature enablement of the
following features:
1.FEAT_AMUv1p1 - ENABLE_FEAT_AMUv1p1
2.FEAT_CSV2_2  - ENABLE_FEAT_CSV2_2
3.FEAT_VHE     - ENABLE_FEAT_VHE
4.FEAT_DIT     - ENABLE_FEAT_DIT
5.FEAT_SB      - ENABLE_FEAT_SB
6.FEAT_SEL2    - ENABLE_FEAT_SEL2

Also as part of feature detection mechanism, we now support three
states for each of these features, allowing the flags to take either
(0 , 1 , 2) values. Henceforth the existing feature build options are
converted from boolean to numeric type and is updated accordingly
in this patch.

The build flags take a default value and will be internally enabled
when they become mandatory from a particular architecture version
and upwards. Platforms have the flexibility to overide this
internal enablement via this feature specific explicit build flags.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I0090c8c780c2e7d1a50ed9676983fe1df7a35e50
2022-04-05 17:34:17 +01:00
Manish Pandey 1bbe2135c3 Merge "fix(st): remove extra chars from dtc version" into integration 2022-04-05 11:31:14 +02:00
Yann Gautier 03d20776ef fix(st): remove extra chars from dtc version
In some implementations of dtc tool (e.g. with yocto), there can be a 'v'
at the beginning of the version, and a '+' at the end. Just keep numbers
then, with a grep -o.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I180e97ab75ba3e5ceacb4b1961a1f22788b428a3
2022-04-05 08:58:16 +02:00
Jayanth Dodderi Chidanand 0ce220afb2 refactor(el3-runtime): replace ARM_ARCH_AT_LEAST macro with FEAT flags
Replacing ARM_ARCH_AT_LEAST macro with feature specific build options
to prevent unconditional accesses to the registers during context save
and restore routines.

Registers are tightly coupled with features more than architecture
versions. Henceforth having a feature-specific build flag guarding the
respective registers, will restrict any undefined actions.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I809774df580530803c8a6e05a62d8d4de0910e02
2022-04-04 10:25:02 +01:00
Jayanth Dodderi Chidanand 6a0da73647 refactor(el3-runtime): add arch-features detection mechanism
This patch adds architectural features detection procedure to ensure
features enabled are present in the given hardware implementation.

It verifies whether the architecture build flags passed during
compilation match the respective features by reading their ID
registers. It reads through all the enabled feature specific ID
registers at once and panics in case of mismatch(feature enabled
but not implemented in PE).

Feature flags are used at sections (context_management,
save and restore routines of registers) during context switch.
If the enabled feature flag is not supported by the PE, it causes an
exception while saving or restoring the registers guarded by them.

With this mechanism, the build flags are validated at an early
phase prior to their usage, thereby preventing any undefined action
under their control.

This implementation is based on tristate approach for each feature and
currently FEAT_STATE=0 and FEAT_STATE=1 are covered as part of this
patch. FEAT_STATE=2 is planned for phase-2 implementation and will be
taken care separately.

The patch has been explicitly tested, by adding a new test_config
with build config enabling majority of the features and detected
all of them under FVP launched with parameters enabling v8.7 features.

Note: This is an experimental procedure and the mechanism itself is
      guarded by a macro "FEATURE_DETECTION", which is currently being
      disabled by default.

The "FEATURE_DETECTION" macro is documented and the platforms are
encouraged to make use of this diagnostic tool by enabling this
"FEATURE_DETECTION" flag explicitly and get used to its behaviour
during booting before the procedure gets mandated.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ia23d95430fe82d417a938b672bfb5edc401b0f43
2022-04-04 10:24:51 +01:00
Joanna Farley f78cb61a11 Merge changes I84e257b3,I1317e482 into integration
* changes:
  fix(layerscape): fix coverity issue
  fix(nxp-ddr): fix coverity issue
2022-03-30 09:38:52 +02:00
Jiafei Pan 5161cfde9b fix(layerscape): fix coverity issue
Check return value of mmap_add_dynamic_region().

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I84e257b3052371e18af158c3254f42a1bae0da10
2022-03-30 10:38:22 +08:00
Joanna Farley e24ce2c1c8 Merge "fix(scmi): use same type for message_id" into integration 2022-03-29 17:01:48 +02:00
Jiafei Pan f713e5954e fix(nxp-ddr): fix coverity issue
Check return value of mmap_add_dynamic_region().

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1317e4822f3da329185d54005f08047872b5cdce
2022-03-29 14:43:12 +08:00
Joanna Farley 0263c968a7 Merge changes Ic1796898,I93bd392a into integration
* changes:
  fix(errata): workaround for Cortex A78 AE erratum 2395408
  fix(errata): workaround for Cortex A78 AE erratum 2376748
2022-03-29 00:21:37 +02:00
Soby Mathew ad88c37080 Merge changes from topic "rme-attest" into integration
* changes:
  feat(rme): add dummy realm attestation key to RMMD
  feat(rme): add dummy platform token to RMMD
2022-03-28 18:32:27 +02:00
Joanna Farley 2ea18c7df3 Merge changes from topics "ls1088a", "ls1088a-prepare" into integration
* changes:
  docs(layerscape): add ls1088a soc and board support
  feat(ls1088aqds): add ls1088aqds board support
  feat(ls1088ardb): add ls1088ardb board support
  feat(ls1088a): add new SoC platform ls1088a
  build(changelog): add new scopes for ls1088a
  feat(bl2): add support to separate no-loadable sections
  refactor(layerscape): refine comparison of inerconnection
  feat(layerscape): add soc helper macro definition for chassis 3
  feat(nxp-gic): add some macros definition for gicv3
  feat(layerscape): add CHASSIS 3 support for tbbr
  feat(layerscape): define more chassis 3 hardware address
  feat(nxp-crypto): add chassis 3 support
  feat(nxp-dcfg): add Chassis 3 support
  feat(lx2): enable DDR erratas for lx2 platforms
  feat(layerscape): print DDR errata information
  feat(nxp-ddr): add workaround for errata A050958
  feat(layerscape): add new soc errata a010539 support
  feat(layerscape): add new soc errata a009660 support
  feat(nxp-ddr): add rawcard 1F support
  fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
  fix(nxp-tools): fix create_pbl print log
  build(changelog): add new scopes for NXP driver
2022-03-28 17:40:59 +02:00
Soby Mathew a0435105f2 feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
parameters:
    * Fid (0xC400001B2).
    * Attestation key buffer PA (the realm attestation key is copied
      at this address by the monitor).
    * Attestation key buffer length as input and size of realm
      attesation key as output.
    * Type of elliptic curve.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I12d8d98fd221f4638ef225c9383374ddf6e65eac
2022-03-28 15:02:01 +02:00
Manish Pandey 62a63491de Merge "fix(fwu): rename is_fwu_initialized" into integration 2022-03-28 13:59:23 +02:00
Manish Pandey 869dd20ff7 Merge "docs(maintainers): add the new maintainer for MediaTek SoCs" into integration 2022-03-28 12:41:46 +02:00
Rex-BC Chen 933bf32c14 docs(maintainers): add the new maintainer for MediaTek SoCs
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia9409127e91e55726db0856e3f13f009d3c7c866
2022-03-28 17:49:31 +08:00
Sebastien Pasdeloup aae7c96de6 fix(fwu): rename is_fwu_initialized
The variable is_fwu_initialized was initialized after
plat_fwu_set_images_source() is called.
But some functions called by plat_fwu_set_images_source() for STM32MP1
implementation expect is_fwu_initialized is set to true with asserts.
Rename is_fwu_initialized to is_metadata_initialized, and set it before
plat_fwu_set_images_source() is called.

Change-Id: I17c6ee6293dfa55385b0c859db442647f0bebaed
Signed-off-by: Sebastien Pasdeloup <sebastien.pasdeloup-ext@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-03-28 09:10:11 +02:00
Jiafei Pan 6e4e294a07 docs(layerscape): add ls1088a soc and board support
Update document for nxp-layerscape to add ls1088a SoC and ls1088ardb,
update maintainer of ls1088a platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ic7fdc7b1bbf22e50646991093366a88ee523ffe3
2022-03-27 23:24:24 +08:00
Jiafei Pan 0b0e676698 feat(ls1088aqds): add ls1088aqds board support
Add QDS support for ls1088a.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6c7a7a23fa6b9ba01c011a7e6237f8063d45e261
2022-03-27 23:24:24 +08:00
Jiafei Pan 2771dd0293 feat(ls1088ardb): add ls1088ardb board support
The LS1088A reference design board provides a comprehensive platform
that enables design and evaluation of the product (LS1088A processor).

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If4ca24fcee7a4c2c514303853955f1b00298c0e5
2022-03-27 23:24:24 +08:00
Jiafei Pan 9df5ba05b4 feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated
SoC device featuring eight extremely power-efficient 64-bit ARM
Cortex-A53 cores with ECC-protected L1 and L2 cache memories for
high reliability, running up to 1.6 GHz.

This patch is to add ls1088a SoC support in TF-A.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
2022-03-27 23:24:24 +08:00
Jiafei Pan ccb71e33eb build(changelog): add new scopes for ls1088a
Add new scopes for ls1088a SoC, RDB and QDS boards.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I7c0018ecee3c590253cf258851a28c4dd7f9c1a1
2022-03-27 23:24:24 +08:00
Jiafei Pan 96a8ed14b7 feat(bl2): add support to separate no-loadable sections
Add new options SEPARATE_BL2_NOLOAD_REGION to separate no-loadable
sections (.bss, stack, page tables) to a ram region specified
by BL2_NOLOAD_START and BL2_NOLOAD_LIMIT.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I844ee0fc405474af0aff978d292c826fbe0a82fd
2022-03-27 23:24:24 +08:00
Biwen Li ceae374357 refactor(layerscape): refine comparison of inerconnection
Refine the code to be compatible with new CCN504 which is used
by ls2088a.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2e2b3bbb9392862b04bf8a89dfb9575bf4be974a
2022-03-27 23:24:24 +08:00
Jiafei Pan 602cf53b6f feat(layerscape): add soc helper macro definition for chassis 3
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I27b3a1f597de84dc2a007798e54eb919c877281a
2022-03-27 23:24:24 +08:00
Biwen Li 9755fd2ec2 feat(nxp-gic): add some macros definition for gicv3
Add macros as follows,
    - GICD_ISENABLER_1
    - GICD_ISENABLER_3
    - GICD_ICENABLER_1
    - GICD_ICENABLER_3

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia522ab4bc496d9a47613a49829b65db96e2b1279
2022-03-27 23:24:24 +08:00
Biwen Li 9550ce9ddd feat(layerscape): add CHASSIS 3 support for tbbr
Support CHASSIS 3.0(such as SoC LS1088A).

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I60843bc4d604f0de1d91c6d3ad5eb4921cdcc91a
2022-03-27 23:24:24 +08:00
Jiafei Pan 0d396d6455 feat(layerscape): define more chassis 3 hardware address
Add base address definiton for Chassis 3 platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6041b93c9e9bb49af60743bd277ac7cc6f1b9da8
2022-03-27 23:24:24 +08:00
Jiafei Pan d60364d48e feat(nxp-crypto): add chassis 3 support
Add Chassis 3 support for CAAM driver.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ied26dd3881489a03017a45966888a61a0813492c
2022-03-27 23:24:24 +08:00
Biwen Li df02aeeec6 feat(nxp-dcfg): add Chassis 3 support
Add support for Chassis 3.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799ae173aa23a
2022-03-27 23:24:24 +08:00
Jiafei Pan cd960f5009 feat(lx2): enable DDR erratas for lx2 platforms
Enable DDR erratas for lx2 platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ia2cf6ed077acf81882247153ec38bda708a6f007
2022-03-27 23:24:24 +08:00
Jiafei Pan 3412716b30 feat(layerscape): print DDR errata information
Print Errata information in debug mode.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I70d6baa4dc3ffd79fedbc827555268d8f06605c7
2022-03-27 23:24:24 +08:00
Pankit Garg 291adf521a feat(nxp-ddr): add workaround for errata A050958
Set the receiver gain to max value to recover
cold temp marginality issue for phy-gen2

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: If639fa3ed404cf6e1b8abcc2b7137db1fdd0b2c2
2022-03-27 23:24:24 +08:00
Jiafei Pan 85bd092943 feat(layerscape): add new soc errata a010539 support
Add new soc errata a010539 support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Idbd8caaac12da8ab4f39dc0019cb656bcf4f3401
2022-03-27 23:24:24 +08:00
Jiafei Pan 785ee93cc3 feat(layerscape): add new soc errata a009660 support
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ice37155d971dec5c610026043e34b64f761fc1b7
2022-03-27 23:24:24 +08:00
Maninder Singh f2de48cb14 feat(nxp-ddr): add rawcard 1F support
New UDIMM 18ADF2G72AZ-2G6E1 has raw card ID = 0x1F

Also, changing mask for raw card ID from - 0x8f -> 0x9f

Changing the mask need the raw card to changed from 0x0f -> 0x1f

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iee8e732ebc5e09cdca6917be608f1597c7edd9f9
2022-03-27 23:24:24 +08:00
Biwen Li e2818d0afc fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
Fix build issue of mmap_add_ddr_region_dynamically():
ls_bl2_el3_setup.c:(.text.bl2_plat_preload_setup+0x28): undefined
reference to mmap_add_ddr_region_dynamically

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I74a8b4c2337fc0646d6acb16ce61755c5efbdf38
2022-03-27 23:24:24 +08:00
Biwen Li 31af441a04 fix(nxp-tools): fix create_pbl print log
Replace bl2_offset with bl2_loc, and fix byte-swapping for
Chassis2 SoC(s) only.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ieb5fd6468178325bfb6fb89b6c31c75cd9030363
2022-03-27 23:24:24 +08:00