Commit Graph

9752 Commits

Author SHA1 Message Date
Manish Pandey 73193689c0 Merge changes I7c9f8490,Ia92c6d19 into integration
* changes:
  feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
  feat(plat/mediatek/mt8195): dump EMI MPU configurations
2021-12-06 16:47:33 +01:00
Tinghan Shen 690cb1265e feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204347737
TEST=build pass

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc
2021-12-06 15:29:08 +08:00
Tinghan Shen 20ef588e86 feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2021-12-06 15:29:06 +08:00
Manish Pandey 8a63739b31 Merge "fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds" into integration 2021-12-03 15:12:21 +01:00
Madhukar Pappireddy 1777ac11a5 Merge changes I8990bce2,Iacef5e67,I2976c0a4,I8551a802 into integration
* changes:
  fix(plat/marvell/a3720/uart): do external reset during initialization
  feat(plat/marvell/a3k): add north and south bridge reset registers
  fix(plat/marvell/a3720/uart): configure UART after TX FIFO reset
  feat(plat/marvell/a3720/uart): preserve x1/x2 regs in console_a3700_core_init()
2021-12-02 20:54:27 +01:00
Pali Rohár 0ee80f35a2 fix(plat/marvell/a3720/uart): do external reset during initialization
Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from TX FIFO anymore
and TX FIFO stays always empty. TX FIFO reset does not recover UART HW
from this broken state.

Experiments show that external reset can fix UART HW from this broken
state.

TF-A fatal error handler calls console_a3700_core_init() function to
initialize UART HW. This handler may be called anytime during CPU
runtime, also when kernel is running.

U-Boot or Linux kernel may change UART clock to TBG to achieve higher
baudrates. During initialization, console_a3700_core_init() resets UART
configuration to default settings, which means that it also changes
UART clock from TBG to XTAL.

Do an external reset of UART via North Bridge Peripheral reset register
to prevent this UART hangup.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8990bce24d1a6fd8ccc47a2cd0a5ff932fcfcf14
2021-12-02 17:38:02 +01:00
Pali Rohár a4d35ff381 feat(plat/marvell/a3k): add north and south bridge reset registers
These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular bit,
but some need setting the bit. Reflect this via "_N" suffix in macro
names.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc
2021-12-02 17:37:58 +01:00
Pali Rohár 15546dbf40 fix(plat/marvell/a3720/uart): configure UART after TX FIFO reset
If TX FIFO is not empty, do not touch UART settings and let UART HW
transmit remaining bytes from TX FIFO. New UART settings are then set
only after TX FIFO is reset.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2976c0a4fbb841d3a79d42ef67c06e70174afc3b
2021-12-02 17:37:54 +01:00
Pali Rohár 7c85a75729 feat(plat/marvell/a3720/uart): preserve x1/x2 regs in console_a3700_core_init()
Followup changes will need function arguments in registers x0, x1 and
x2. Do not modify x1 and x2 registers and instead use scratch x3 and x4
registers for storing local variables.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8551a802995f39128d2f4a8f8076b5bf463d0db0
2021-12-02 17:37:49 +01:00
Vijayenthiran Subramaniam 78d7e81979 fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds
Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is set to
0 when SPM_MM build is enabled. To support SPM_MM builds on SGI/RD
platforms set ENABLE_SVE_FOR_NS to 0.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If78ed7567f6d988795b2bc7f772a883783246964
2021-12-02 08:27:51 +01:00
Manish Pandey 29ad12a7b5 Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration
* changes:
  fix(plat/xilinx/versal): resolve misra R10.6
  fix(plat/xilinx/versal): resolve misra R14.4
  fix(plat/xilinx/versal): resolve misra R17.7
  fix(plat/xilinx/versal): resolve misra R10.3
  fix(plat/xilinx/versal): resolve misra R7.2
  fix(plat/xilinx/versal): resolve misra R15.7
  fix(plat/xilinx/versal): resolve misra R15.6
  fix(plat/xilinx/versal): resolve misra R10.1 in pm services
  fix(plat/xilinx/versal): resolve misra R20.7 in pm services
  fix(plat/xilinx/versal): resolve misra R10.3 in pm services
  fix(plat/xilinx/versal): resolve misra R10.6 in pm services
  fix(plat/xilinx/versal): resolve misra R16.3 in pm services
  fix(plat/xilinx/versal): resolve misra R15.6 in pm services
2021-12-01 17:52:30 +01:00
Manish Pandey e75286a8a0 Merge changes from topic "fix_pie" into integration
* changes:
  fix(pie): align fixup_gdt_reloc() for aarch64
  fix(pie): do not skip __RW_END__ address during relocation
2021-12-01 17:39:17 +01:00
Yann Gautier 5ecde2a271 fix(pie): align fixup_gdt_reloc() for aarch64
Do not skip upper limit address (__RW_END__) during relocation process.
This align the code on what is done for AARCH32.

Change-Id: I236368376276c2d3aa79adce13ca49f4023ce369
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-01 17:35:33 +01:00
Yann Gautier 4f1a658f89 fix(pie): do not skip __RW_END__ address during relocation
In fixup_gdt_reloc(), do not skip the last address (__RW_END__) for
dynamic relocations.
Else, the invalidation of the data done under _init_c_runtime in
el3_entrypoint_common macro will not be correct.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1166a59ac964ec8ad4e099cb3600e843afc71d82
2021-12-01 17:35:27 +01:00
Manish Pandey e018bf719b Merge "feat(mt8186): initialize platform for MediaTek MT8186" into integration 2021-12-01 17:14:04 +01:00
Rex-BC Chen 27132f13ca feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
2021-12-01 16:36:28 +01:00
Manish Pandey a142dc9698 Merge "fix(commitlint): change scope-case to lower-case" into integration 2021-12-01 15:39:59 +01:00
Manish Pandey 2141a68543 Merge changes I0c1f7d6c,I3bec0b58,If24cf213 into integration
* changes:
  feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
  feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
  feat(plat/mediatek/apu): add mt8195 APU iommap regions
2021-12-01 14:21:50 +01:00
Yann Gautier 804e52e9a7 fix(commitlint): change scope-case to lower-case
This avoids errors when mixing letters and numbers in the scope.

Change-Id: Icd2151d5b42b02ced0d801691ffb5997f4be2a1e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-11-30 19:01:59 +01:00
Manish Pandey 93adf93047 Merge "feat(plat/qemu): add SPMD support with SPMC at S-EL1" into integration 2021-11-30 11:36:13 +01:00
Abhyuday Godhasara 93d4625627 fix(plat/xilinx/versal): resolve misra R10.6
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
  with wider essential type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Ia0d13c3cfeb13d22b6fc7e8869cc713218302973
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara a62c40d427 fix(plat/xilinx/versal): resolve misra R14.4
MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
  expression of an iteration-statement shall have essentially Boolean type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I8cf821a42015858200cc0c514600012c8f61061f
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 526a1fd147 fix(plat/xilinx/versal): resolve misra R17.7
MISRA Violation: MISRA-C:2012 R.17.7
- The value returned by a function having non-void return type shall be
  used ((void) missing for discarded return value.).

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I1e6a598b9fe6c571a3e5010ee832ef860dfe491d
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara b2bb3efb8f fix(plat/xilinx/versal): resolve misra R10.3
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
  narrower essential type or of a different essential type category

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I9c6dd8dba40db8067b46947ceff295732648612a
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 0623dcea0f fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
  represented in an unsigned type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara bc2637e379 fix(plat/xilinx/versal): resolve misra R15.7
MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated with an else statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iea32e32b5683f7accd7fac8d557957f05ed0f5c5
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara b9fa2d9fc1 fix(plat/xilinx/versal): resolve misra R15.6
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: If1ccaa2f254ac85a329295de501e2b5558e8ff43
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 775bf1bbd3 fix(plat/xilinx/versal): resolve misra R10.1 in pm services
MISRA Violation: MISRA-C:2012 R.10.1
- Operands shall not be of an inappropriate essential type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67b5788054a136be8d764472c5d85528a5c4272f
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 5dada6227b fix(plat/xilinx/versal): resolve misra R20.7 in pm services
MISRA Violation: MISRA-C:2012 R.20.7
- Expressions resulting from the expansion of macro parameters shall be
  enclosed in parentheses

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Id913c556cab955c798809ad2bd08ca3e48e2231a
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 5d1c211e22 fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
  narrower essential type or of a different essential type category

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I73c056ff4df2f14e04c92a49ac5c97e578e82107
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara fa98d7f2f8 fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
  with wider essential type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67ac6b6b4b643f57e76a435345540e241c9a88b9
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 27ae531088 fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I576b2c6eb7d1b7ef20440b9a616886ccf230b63e
2021-11-30 01:59:34 -08:00
Abhyuday Godhasara 4156719550 fix(plat/xilinx/versal): resolve misra R15.6 in pm services
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I82e924a77ee3afeb56fa18714e94cc4f6fff5a49
2021-11-30 01:54:51 -08:00
Flora Fu 296b590206 feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
2021-11-30 09:34:05 +08:00
Flora Fu 88906b4437 feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e9568c0150436afa42
2021-11-30 09:23:46 +08:00
Flora Fu 339e4924a7 feat(plat/mediatek/apu): add mt8195 APU iommap regions
Add APU iommap settings for reviser, apu_ao and
clock/pll register ranges.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If24cf21318813babfc2c11f38891521c7106b58c
2021-11-30 09:09:31 +08:00
Jens Wiklander f58237ccd9 feat(plat/qemu): add SPMD support with SPMC at S-EL1
Adds support for SPMD with SPMC at S-EL1. A new config option SPMC_OPTEE
is added to support loading the special OP-TEE images when configured
with SPD=spmd. With or without SPMC_OPTEE. It should still be possible
to load another BL32 payload implementing a SPMC, provided that entry
point is the same as load address, that is, BL32_BASE.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: Ie61dcd1ee564688baee1b575030e63dc2bb85121
2021-11-29 13:57:57 +01:00
Olivier Deprez d605439900 Merge "docs(spm): update threat model with FF-A v1.1" into integration 2021-11-26 09:58:13 +01:00
Soby Mathew 2845a68703 Merge "fix(rmmd): preserve x4-x7 as per SMCCCv1.1" into integration 2021-11-24 18:49:18 +01:00
Soby Mathew 11578303fd fix(rmmd): preserve x4-x7 as per SMCCCv1.1
The RMI command handling in RMMD did not preserve x4 to x7 when
returning to NS caller. Although this is allowed for SMCCCv1.0, this is
not correct as per v1.1. This fixes the same by differentiating the
onward and backward path during SMC handling.

This patch also fixes an issue with the backward path wherein the first
argument was being truncated to 32 bits.

Change-Id: Ibc85d574d5a2178a763975ddb32e456a12e7dc88
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2021-11-24 19:26:51 +02:00
J-Alves 668ce500f9 docs(spm): update threat model with FF-A v1.1
Update SPM's threat model to contain threats related to notifications
feature, compliant with FF-A v1.1 spec.

Change-Id: I4a825be5dd14137a0d04d532adfe5343714794c5
Signed-off-by: J-Alves <joao.alves@arm.com>
2021-11-23 17:30:40 +00:00
Manish Pandey a1f02f4f3d Merge "docs(changelog): generate changelog" into integration 2021-11-23 14:14:26 +01:00
Manish V Badarkhe 63d2e96042 docs(changelog): generate changelog
For future reference, this changelog was generated with the following
command:

    npm run release -- --skip.commit --skip.tag --release-as 2.6.0

Change-Id: Idf6be5c3be15ddfdb1d32fafb9e0e4b399b269f3
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-11-22 23:08:12 +00:00
Olivier Deprez f92b00187a Merge "docs(ff-a): update documentation of FF-A interfaces" into integration 2021-11-22 18:38:07 +01:00
Manish Pandey 5d26e27abc Merge changes from topic "ck/changelog" into integration
* changes:
  docs(changelog): categorize scopes
  docs(commit-style): add commit style documentation
  build(docs): introduce release script
  build(docs): add support for Markdown documentation
  build(hooks): add commitlint checks for trailers
  build(npm): add Standard Version v9.3.2
  build(npm): add additional package metadata
  build(npm): add license field
  build(npm): update Husky to v7.0.4
  build(npm): update commitlint to v14.1.0
  build(npm): update lockfile format to v2
  docs(prerequisites): update to Node.js v16
  build(docs): update Python dependencies
  build(docs): pin Python dependencies
2021-11-18 16:00:01 +01:00
J-Alves 16c1c45326 docs(ff-a): update documentation of FF-A interfaces
- Overview of FF-A v1.1 notifications feature, and list of all
the new related interface.
- FFA_RXTX_UNMAP now implemented, so provided description.
- FF-A v1.1 interfaces documented: FFA_SPM_ID_GET and
FFA_SECONDARY_EP_REGISTER.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If40b4d2b2473f81ecfb2ddbf14852c3f10682867
2021-11-18 14:41:28 +00:00
Manish Pandey 7300434afc Merge "fix(drivers/gic600ae_fmu): fix timeout calculation" into integration 2021-11-18 15:25:14 +01:00
Manish Pandey b3e2b6e715 Merge "fix(docs): fix `FF-A` substitution" into integration 2021-11-18 14:07:08 +01:00
anzhou 7f322f228e fix(drivers/gic600ae_fmu): fix timeout calculation
The previous codes were using the cntpct_el0 to check the time
elapsed. But this physical timer does not seem to count for
the expected time resulting in gic fmu communication failures
on Tegra platforms.

This patch uses the delay_timer instead to use a platform
defined timer for calculating timeouts.

Change-Id: Ic8646ad1662c9928ac64c4152deb27e8c86fe344
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2021-11-18 13:36:50 +02:00
Sandrine Bailleux c0db39cefc Merge "fix(plat/arm): fix a VERBOSE trace" into integration 2021-11-18 10:28:20 +01:00