Commit Graph

8176 Commits

Author SHA1 Message Date
Manish Pandey aa47d59d40 Merge "rcar_gen3: drivers: console: Treat log as device memory" into integration 2020-12-08 23:02:36 +00:00
Manish Pandey f0f3d3687b Merge changes from topic "zynqmp-bug-fixes" into integration
* changes:
  zynqmp: pm: Update flags in common clk divisor node
  zynqmp: pm_api_clock: Copy only the valid bytes
2020-12-08 22:53:13 +00:00
Marek Vasut 605767475e rcar_gen3: drivers: console: Treat log as device memory
The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.

The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
2020-12-08 22:27:13 +00:00
Ravi Patel c8f6253683 zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
 Consider a case of nand_ref clock which has 2 divisor and 1 mux.
 The frequency of mux clock is 1500MHz and default value of div1 and
 div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
 When driver requests 80MHz for nand_ref clock, clock framework will
 adjust the div2 value to 1 (setting div2 value 2 results final clock
 to 50MHz which is more inaccurate compare to 100Mhz) which results
 final clock to 100MHz.
 Ideally the value of div1 and div2 should be updated to 19 and 1
 respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
2020-12-08 22:24:44 +00:00
Siva Durga Prasad Paladugu f2afaad071 zynqmp: pm_api_clock: Copy only the valid bytes
This patches copies only the valid part of string and
avoids filling junk at the end.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7
2020-12-08 22:24:36 +00:00
Manish Pandey 77990838a4 Merge changes Ibbee37c8,Ic3a13c83,Ib7f2380a,I83b477fd,I284956d4, ... into integration
* changes:
  mediatek: mt8192: dcm: Add mcusys related dcm drivers
  mediatek: mt8192: add ptp3 driver
  mediatek: mt8192: Add SiP service
  mediatek: mt8192: add uart save and restore api
  mediatek: mt8192: modify sys_cirq driver
  mediatek: mt8192: add power-off support
  mediatek: mt8192: add pmic mt6359p driver
  mediatek: mt8192: Initialize delay_timer
  mediatek: mt8192: enable NS access for systimer
  mediatek: mt8192: Add CPU hotplug and MCDI support
  mediatek: mt8192: Add MCDI drivers
  mediatek: mt8192: Add SPMC driver
2020-12-08 16:29:52 +00:00
Nina Wu 43d7bbcc6c mediatek: mt8192: dcm: Add mcusys related dcm drivers
1. Add mcusys related dcm drivers
2. Turn on mcusys-related dcm by default

Change-Id: Ibbee37c87cc38e7a6cd7c93c2fc0817aad6dbe95
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-12-07 23:31:19 +00:00
elly.chiang 8709c939d8 mediatek: mt8192: add ptp3 driver
enable PTP3 for protecting sysPi

Signed-off-by: elly.chiang <elly.chiang@mediatek.com>
Change-Id: Ic3a13c8314f829dca8547861b98639d1d9444eb2
2020-12-07 23:31:05 +00:00
Nina Wu 189f038f55 mediatek: mt8192: Add SiP service
Add the basic SiP service

Change-Id: Ib7f2380aab910adf8d33498a79ecd287273907c5
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-12-07 23:30:43 +00:00
Yuchen Huang bb28dc7aea mediatek: mt8192: add uart save and restore api
When system resume, we want to print log as soon as possible.
So we add uart save and restore api, and they will be called
when systtem suspend and resume.

Change-Id: I83b477fd2b39567c9c6b70534ef186993f7053ae
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.com>
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
2020-12-07 23:30:27 +00:00
G.Pangao 49fd68abe4 mediatek: mt8192: modify sys_cirq driver
1.Modify this driver to make it more complete and more standard.
2.And makes this driver available for more IC services.
3.Solve some bugs in the software.

Signed-off-by: G.Pangao <gtk_pangao@mediatek.com>
Change-Id: I284956d47ebbbd550ec93767679181185e442348
2020-12-07 23:30:14 +00:00
Hsin-Hsiung Wang 26f3dbe2d6 mediatek: mt8192: add power-off support
add power-off support

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: If19e99971515a8ae1ac9ae21046e4382adc18a69
2020-12-07 23:29:47 +00:00
Hsin-Hsiung Wang cbd6331beb mediatek: mt8192: add pmic mt6359p driver
add pmic mt6359p driver

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I20f2218f7d2087e8d2bf31258cf92a02e0dab77d
2020-12-07 23:28:48 +00:00
Nina Wu 95cc889488 mediatek: mt8192: Initialize delay_timer
Init delay_timer for the use of delay functions

Change-Id: I35aefd7515bb9259634c8b6bc37d8c74da96e8f1
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
2020-12-07 23:28:33 +00:00
Dehui Sun f3fbacaa9a mediatek: mt8192: enable NS access for systimer
Enable NS access for all systimers.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I3693997082a1d6f09fef5a79b6cf5a91be46cb8a
2020-12-07 23:28:05 +00:00
James Liao 82c00c2ff5 mediatek: mt8192: Add CPU hotplug and MCDI support
Implement PSCI platform OPs to support CPU hotplug and MCDI.

Change-Id: I31abfc752b69ac40e70bc9e7a55163eb39776c44
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2020-12-07 23:27:40 +00:00
James Liao 271d9497dc mediatek: mt8192: Add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.

Change-Id: I5110461e8eef86f8383b45f197ec5cb10dbfeb3e
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2020-12-07 23:27:19 +00:00
James Liao 3d1e536eea mediatek: mt8192: Add SPMC driver
Add SPMC driver for CPU power on/off.

Change-Id: I526b98d5885855efce019dd09cfd93b8816cbf19
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2020-12-07 23:26:41 +00:00
Madhukar Pappireddy 0b18d5a5d6 Merge changes from topic "zynqmp-misc-enhancement" into integration
* changes:
  plat: xilinx: zynqmp: Enable log messages for debug
  plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
2020-12-07 18:13:50 +00:00
Manish Pandey cd6eaab627 Merge changes from topic "marvell-a3k-makefile" into integration
* changes:
  plat: marvell: armada: a3k: Simplify check if WTP variable is defined
  plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
  plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
  plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
  plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
  plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
  plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
  plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
  plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
2020-12-07 11:29:46 +00:00
Pali Rohár e33370828d plat: marvell: armada: a3k: Simplify check if WTP variable is defined
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ieb352f0765882efdcb64ef54e6b2a39768590a06
2020-12-07 11:06:36 +00:00
Pali Rohár bc1f368743 plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
These two targets are build by make subprocesses and are independent.
So splitting them into own targets allow make to build them in parallel.
$(TIMBUILD) script depends on $(TIMDDRTOOL) so specify it in Makefile.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I139fc7fe64d8de275b01a853e15bfb88c4ff840d
2020-12-07 11:06:13 +00:00
Pali Rohár 23b1be79d7 plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
Add check when building mrvl_bootimage that size of bl1 image is not bigger
than maximal size.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib873debd3cfdba9acd4c168ee37edab3032e9f25
2020-12-07 11:05:53 +00:00
Pali Rohár e4bbd39c65 plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile target which specify
non-file targets and therefore needs to be always rebuilt.

Targets clean, realclean and distclean are .PHONY targets used to remove
built files. Correctly set that mrvl_clean target is prerequisite for these
clean targets to ensure that built files are removed.

Finally this change with usage of FORCE target allows to remove mrvl_clean
hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used
just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2fa8971244b43f101d846fc433ef7b0b6f139c92
2020-12-07 11:05:27 +00:00
Pali Rohár ed9bae6ad5 plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id766db4a900a56c795fe5ffdd8a2b80b1aaa2132
2020-12-07 11:05:20 +00:00
Pali Rohár bafc9476b9 plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaecd6c24bf334a959ac2bf395c3ee49c810b01a7
2020-12-07 11:05:14 +00:00
Pali Rohár 2f852b89b1 plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
Create copy of WTMI images instead of moving them into TF-A build directory.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc24c33b9ce540e4acde51fc1a5c946ae66a5d7
2020-12-07 11:05:09 +00:00
Pali Rohár 13aa895623 plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
Rather create a temporary copy in $(BUILD_PLAT) and modify only copy.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I256c029106ea6f69faa086fc4e5bee9f68cd257f
2020-12-07 11:05:04 +00:00
Pali Rohár bdcd1bd0a5 plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
$(WTMI_IMG) is used only by $(MAKE) subprocess in $(DOIMAGEPATH) directory.
So calling truncate on $(WTMI_IMG) after $(MAKE) in $(DOIMAGEPATH) has no
effect and can just damage input file for future usage. Therefore remove
this truncate call.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9925c54c5d3d10eadc19825c5565ad4598a739a7
2020-12-07 11:04:58 +00:00
Venkatesh Yadav Abbarapu 490d81d2fa plat: xilinx: zynqmp: Enable log messages for debug
Save some space by enabling the log messages like bl33 address
only for debug builds. Also check the bl33 and bl32 address and
print only if this is not NULL.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I58d846bf69a75e839eb49abcbb9920af13296886
2020-12-06 21:46:24 -08:00
Tejas Patel a7379a2ab1 plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG
For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. So, change its name from PM_BOOT_HEALTH_STATUS_REG
to PMU_GLOBAL_GEN_STORAGE4.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I2f5c4c6a161121e7cdb4b9f0f8711d0dad16c372
2020-12-06 21:46:03 -08:00
Madhukar Pappireddy 7fc19b8ea9 Merge "qemu/qemu_sbsa: increase SHARED_RAM_SIZE" into integration 2020-12-07 03:40:39 +00:00
Madhukar Pappireddy 307f3b90c7 Merge "plat: xilinx: zynqmp: Include GICv2 makefile" into integration 2020-12-05 23:28:25 +00:00
Venkatesh Yadav Abbarapu 84f2e34fee plat: xilinx: zynqmp: Include GICv2 makefile
Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done in the commit #1322dc94f7.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8
2020-12-03 20:30:37 -07:00
Madhukar Pappireddy 79df6ea430 Merge "plat: xilinx: Use fno-jump-tables flag in CPPFLAGS" into integration 2020-12-03 16:58:59 +00:00
Manish Pandey 49462851aa Merge ".editorconfig: set max line length to 100" into integration 2020-12-03 16:14:40 +00:00
Madhukar Pappireddy 5e5c399de0 Merge "plat: marvell: Update SUBVERSION to match Marvell's forked version" into integration 2020-12-03 15:51:50 +00:00
Yann Gautier 279f77b492 .editorconfig: set max line length to 100
Relax the 80 character line length, as done in checkpatch,
since Linux 5.7.

Change-Id: I093a2e6a45336339193173f7ff6a461279cf411d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2020-12-03 15:39:23 +00:00
Manish Pandey 99ddfc0e46 Merge "Aarch64: Add support for FEAT_PANx extensions" into integration 2020-12-03 13:08:02 +00:00
Olivier Deprez 5e8911a035 Merge "Aarch64: Add support for FEAT_MTE3" into integration 2020-12-03 11:02:26 +00:00
Madhukar Pappireddy 0888694076 Merge "rockchip: Add support for the stack protector" into integration 2020-12-02 18:26:47 +00:00
Alexei Fedorov 0563ab08e8 Aarch64: Add support for FEAT_MTE3
This patch provides the following changes:
- Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register
- Enables Memory Tagging Extension for FEAT_MTE3.

Change-Id: I735988575466fdc083892ec12c1aee89b5faa472
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-12-02 13:53:03 +00:00
Manish Pandey 91cc872c64 Merge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms" into integration 2020-12-02 12:18:02 +00:00
Lauren Wehrmeister 9dd2896e65 Merge "Add support for Neoverse-N2 CPUs." into integration 2020-12-01 17:06:46 +00:00
Masato Fukumori 54b590ec0d qemu/qemu_sbsa: increase SHARED_RAM_SIZE
Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.

sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured with 512 cpus, region size used by qemu is greater
than 4KB.

Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org>
Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36
2020-12-01 14:01:24 +00:00
Christoph Müllner 826ba363c4 rockchip: Add support for the stack protector
It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signed-off-by: Christoph Müllner <christophm30@gmail.com>
2020-12-01 11:54:57 +01:00
Javier Almansa Sobrino 25bbbd2d63 Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-11-30 19:12:56 +00:00
Alexei Fedorov a83103c824 Aarch64: Add support for FEAT_PANx extensions
This patch provides the changes listed below:
- Adds new bit fields definitions for SCTLR_EL1/2 registers
- Corrects the name of SCTLR_EL1/2.[20] bit field from
SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT
- Adds FEAT_PANx bit field definitions and their possible
values for ID_AA64MMFR1_EL1 register.
- Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN
on taking an exception to EL1 in spm_sp_setup() function
(services\std_svc\spm_mm\spm_mm_setup.c)

Change-Id: If51f20e7995c649126a7728a4d0867041fdade19
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-11-30 15:24:52 +00:00
Manish Pandey 9acf573621 Merge changes from topic "xilinx-pm-mainline-linux" into integration
* changes:
  zynqmp: pm: update error codes to match Linux and PMU Firmware
  zynqmp: pm: Filter errors related to clock gate permissions
2020-11-30 12:05:11 +00:00
Manish Pandey 441e7f489f Merge "mediatek: mt8183: add timer V20 compensation" into integration 2020-11-27 11:11:39 +00:00