Disabling filter 0 causes inability to access DRAM.
An attempt leads to an abort.
ARM manual disallows to disable filter 0, but if we do
that from SRAM, nothing bad happens.
This patch prevents disabling of a filter 0, allowing to
reconfigure other filters from DRAM.
Note: this patch doesn't change the logic after reset.
It is only needed in case someone wants to reconfigure the
previously configured TZASC.
Change-Id: I196a0cb110a89afbde97f64a94df3101f28708a4
Signed-off-by: stsp@users.sourceforge.net
Add a new function that allows to enable or disabled filters on
configured regions dynamically. This will avoid the need to
reconfigure the entire attribute and just manage to
enable/disable filters.
Change-Id: If0937ca755bec6c45d3649718147108459682fff
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
The FMU is part of the GIC Distributor (GICD) component. It implements
the following functionality in GIC-600AE:
* Provides software the means to enable or disable a Safety Mechanism
within a GIC block.
* Receives error signaling from all Safety Mechanisms within other GIC
blocks.
* Maintains error records for each GIC block, for software inspection
and provides information on the source of the error.
* Retains error records across functional reset.
* Enables software error recovery testing by providing error injection
capabilities in a Safety Mechanism.
This patch introduces support to enable error detection for all safety
mechanisms provided by the FMU. Platforms are expected to invoke the
initialization function during cold boot.
The support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU
makefile variable. The default value of this variable is '0'.
Change-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.
To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.
Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.
Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the GIC spec or not.
In case of the GIC-600 multichip support we were somewhat abusing that
flag to differentiate between a GIC-700 and GIC-600 implementation
being used in the system.
To avoid a build time dependency on this flag, look at the GICD_IIDR
register and check if the hardware is a GIC-600 or not, to make this
decision at runtime. We then use the values for either GIC-700 or the
GIC-600, respectively.
Change-Id: I8c09ec1cd6fd60d28da879ed55ffef5506f9869d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
For the GIC power management we need to identify certain GIC
implementations, so we have the IIDR values for some Arm Ltd. GIC models
defined.
We will need those number elsewhere very soon, so export them to a
shared header file, to avoid defining them again.
Change-Id: I1b8e2d93d6cea0d066866143c89eef736231134f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z standard)
but upclocked 2.5x. This mode is commonly known under name 2500Base-X.
So remove incorrect SGMII keyword from names and comments and replace it
by more adequate 2500Base-X keyword.
There is no functional change in code, just renaming macros and updating
comments.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If79aec16cc233f4896aafd75bfbbebb3f172a197
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".
Rename occurences of Clayton in comments and macro names to reflect the
official name.
Change-Id: Ie8c55f7da7753127d58c8382b0033c1b486f7909
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM size setting for M3N
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
feat(drivers/rcar3): ddr: add function to judge a DDR rank
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
fix(drivers/rcar3): fix CPG registers redefinition
fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
refactor(plat/rcar3): factor out DT memory node generation
feat(plat/rcar3): add optional support for gzip-compressed BL33
* changes:
feat(io_mtd): offset management for FIP usage
feat(nand): count bad blocks before a given offset
feat(plat/st): add helper to save boot interface
fix(plat/st): improve DDR get size function
refactor(plat/st): map DDR secure at boot
refactor(plat/st): rework TZC400 configuration
NXP drivers header files are moved:
- from: drivers/nxp/<xx>/*.h
- to : include/drivers/nxp/<xx>/*.h
To accommodate these changes each drivers makefiles
drivers/nxp/<xx>/xx.mk, are updated.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
Renamed hw_crc32 to tf_crc32 to make the file and function
name more generic so that the same name can be used in upcoming
software CRC32 implementation.
Change-Id: Idff8f70c50ca700a4328a27b49d5e1f14d2095eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Avoided NV counter update when the system is running in
trial run state.
Change-Id: I5da6a6760f8a9faff777f2ff879156e9c3c76726
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Implemented FWU metadata load and verification APIs.
Also, exported below APIs to the platform:
1. fwu_init - Load FWU metadata in a structure. Also, set the
addresses of updated components in I/O policy
2. fwu_is_trial_run_state - To detect trial run or regular run
state
Change-Id: I67eeabb52d9275ac83be635306997b7c353727cd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
A RAS error may be triggered while offline core in OS. Error:
Uncorrected software error in the Distributor, with IERR=9,SERR=f.
Core put to sleep before its Group enables were cleared.
gicv3_cpuif_disable() will be called in offline core flow.
According to GIC architecture version 3 and version 4:
Architectural execution of a DSB instruction guarantees that
the last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,
ICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed
by the associated Redistributor.
An ISB or other context synchronization operation must precede
the DSB to ensure visibility of System register writes.
Signed-off-by: Ming Huang <huangming@linux.alibaba.com>
Change-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d
One platform may not implement all the protocols, to avoid build break
when we not include all the protocols, add weak functions.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I1485baa2e8f381cb0eede1a7b93ed10e49934971
Add SCMI power domain protocol, with POWER_STATE_NOTIFY and
POWER_STATE_CHANGE_REQUESTED_NOTIFY not implemented.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ia7c4db57c4c702667f8eaa630c924016e4a8bde0
For AARCH64, BIT() will make the number as ULL type, let use BIT_32()
here.
And use %zu for size_t print format.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I1dc18d374cd2c6eb83b40b66ed6189dcc6a21728
A new seek handler is also created. It will be used for NAND to add an
extra offset in case of bad blocks, when FIP is used.
Change-Id: I03fb1588b44029db50583c0b2e7af7a1e88a5a7a
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
In case of FIP, the offsets given in the FIP header are relative.
If bad blocks are found between the FIP base address and this offset,
the offset should be updated, taking care of the bad blocks.
Change-Id: I96fefabb583b3d030ab05191bae7d45cfeefe341
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This commit adds the function to change the settings used for DDR
initialization depending on the board ID and DDR rank.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I94d550cea620748f5b15499fed1b791a69d61592
This commit fixes value to write to the ICCR register according to
the hardware manual.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I1f612a482c012a6739e2f31db80224b222df766c
This commit deletes the value of the redefined CPG register.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
- In add_event2():
Turn the first error condition checking whether there is room for an
extra event2 data structure into an assertion. The platform layer is
responsible for choosing an appropriate event log buffer size based
on the number of measurements it expects. If this assertion fires,
the platform macro EVENT_LOG_SIZE should be adjusted and the
firmware recompiled.
Call this assumption out in the function documentation.
Also remove the second error condition check, which is a subset of
the first one and thus is redundant.
As a result of these changes, add_event2() can no longer fail. Thus,
change its return type from int to void.
Also, the 'size_of_event' local variable is now unused in release
builds so remove it and move its value into the assertion.
Change-Id: I113fc141de59708b20435a0c7126255561ab7786
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
- In event_log_init():
Throughout the function, we are incrementing a pointer by some fixed
amounts of bytes (corresponding to the size of some data structure or
to some constant number of bytes), there is no variable-size
increments in the picture. Thus it seems pointless to verify that the
pointer has indeed been incremented by this fixed amount of bytes
afterwards.
For this reason, remove these checks altogether. As a result, the
start_ptr local variable is now unused so remove it as well.
Change-Id: I612e2278cd3a63d1417427e45d81e285503f5efe
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Weak definitions are confusing and should be avoided if possible.
Thus, turn plat_get_measured_boot_data() into a strong definition that
platforms must provide (if they need measured boot).
We could have moved the old weak implementation under plat/common as a
sane, default implementation that platforms may pull in if it suits
them. However, this implementation right now simply measures BL2,
which is not enough to get a complete measured boot flow, so this
patch just removes it.
This change only affects the Arm FVP platform, as no other upstream
platform implements measured boot at the moment.
Change-Id: If8680a39ae0ef1044ee981315439d5e0c8461229
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Invert test logic on the status register control to
fix issue when the bit SR_QUAD_EN_MX is not set.
Change-Id: I8b2f140219f124336bf96462abf9d9445d0308bc
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
In pmic_operate(), "regulators" node value must be checked before
entering in the fdt_for_each_subnode loop.
Change-Id: I1460cd24ec56ec47ab644f396b71b92973e75fb4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Make sure that i2c->i2c_state is correctly initialized
with I2C_STATE_RESET value this avoid hi2c->lock to not
be set to 0 when calling stm32_i2c_init during platform
suspend/resume operations.
Change-Id: I3b4c1f9115589325eb256789a1764c322741db7d
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The function stm32mp1_clk_init() returns an int. Return a negative
error value if the device tree is not found.
Change-Id: I422d5fea46c4d63d55a5b62e1db154c1f53f41b7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Use helper functions to get SPI and ESPI INTID limit, to remove
several pieces of similar code in gicv3 driver.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: Iaf441fe5e333c4260e7f6d98df6fdd931591976d
Add helper function gicv3_get_espi_limit() to get the value of
(maximum extended SPI INTID + 1), so that some duplicated code can be
removed later.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I0355ca2647f872e8189add259f6c47d415494cce
Add newline(\n) to make the message clearer when the warnings are
really triggered.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I5e2574a52c9065db32ecb4d453b9b02445f69a82
Stas Sergeev
André Przywara
Mark Dykes
Madhukar Pappireddy
Lionel Debieve
Joanna Farley
Varun Wadekar
Pali Rohár
Jiafei Pan
Manish Pandey
Pankaj Gupta
Manish V Badarkhe
Ming Huang
Peng Fan
Yann Gautier
Toshiyuki Ogasahara
Chiaki Fujii
Sandrine Bailleux
Nicolas Le Bayon
Benjamin Gaignard
Yann Gautier
Heyi Guo