Commit Graph

5593 Commits

Author SHA1 Message Date
John Tsichritzis cf57ff8b99 Re-apply GIT_COMMIT_ID check for checkpatch
As it turns out, Gerrit's merge commits don't always respect that format
so these mistakes have to be ignored as false positives.

Change-Id: I4e38d9c34c95588e7916fba4c154f017d8c92dec
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-12 11:06:24 +01:00
Sandrine Bailleux 21bde92ff6 Merge "plat: imx8m: Add caam module init on imx8m" into integration 2019-07-09 12:33:31 +00:00
Sandrine Bailleux a83d8d2ced Merge changes from topic "jts/reword" into integration
* changes:
  docs: removing references to GitHub
  Change checkpatch.conf after migration to tf.org
2019-07-09 12:24:28 +00:00
Sandrine Bailleux 2cbeee4d51 Merge "rpi3: Fix compilation error when stack protector is enabled" into integration 2019-07-08 16:21:01 +00:00
Madhukar Pappireddy f6de960fb7 rpi3: Fix compilation error when stack protector is enabled
Include necessary header file to use ARRAY_SIZE() macro

Change-Id: I5b7caccd02c14c598b7944cf4f347606c1e7a8e7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-07-08 10:45:48 -05:00
John Tsichritzis d012c012e8 docs: removing references to GitHub
Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-08 12:52:33 +01:00
John Tsichritzis 65b5a4b993 Change checkpatch.conf after migration to tf.org
A specific checkpatch setting was used because of GitHub. This necessity
doesn't exist anymore.

Change-Id: Ie2225a5cb88654f3b7407e43e0a48fafa9a9165c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-08 12:47:48 +01:00
Sandrine Bailleux 996d379309 Merge "tools/fiptool: Add Makefile.msvc to build on Windows." into integration 2019-07-05 11:25:17 +00:00
Sandrine Bailleux ef4b8d5a80 Merge "uniphier: support console based on multi-console" into integration 2019-07-05 11:22:09 +00:00
Masahiro Yamada ac9f1b5555 uniphier: support console based on multi-console
The legacy console is gone. Re-add the console support based on the
multi-console framework.

I am still keeping the putc, getc, and flush callbacks in
uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S

The console registration code already relies on that C environment
has been set up. So, I just filled the struct console fields with the
callback pointers, then called console_register() directly. I also
re-implemented the init function in C to improve the readability.

Removing the custom crash console implementation has one disadvantage;
we cannot use the crash console on very early crashes because
crash_console_helpers.S works only after the console is registered.
I can live with this limitation.

Tested on my boards, and confirmed this worked like before.

Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-05 18:43:16 +09:00
Sandrine Bailleux 354e263a2d Merge "ti: k3: common: Trap all asynchronous bus errors to EL3" into integration 2019-07-05 08:05:45 +00:00
Andrew F. Davis 93d5e14130 ti: k3: common: Trap all asynchronous bus errors to EL3
These errors are asynchronous and cannot be directly correlated with the
exact current running software, so handling them in the same EL is not
critical. Handling them in TF-A allows for more platform specific
decoding of the implementation defined exception registers

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda
2019-07-04 12:14:46 -04:00
Jacky Bai 2502709f60 plat: imx8m: Add caam module init on imx8m
CAAM module must be initialized in secure world
before it can be used in non-secure world.

Change-Id: I042893667ddef99d8b6fc3902847d516d8591996
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-07-04 19:59:43 +08:00
Sandrine Bailleux bb2d778c74 Merge changes from topic "lw/n1_errata_fixes" into integration
* changes:
  Removing redundant ISB instructions
  Workaround for Neoverse N1 erratum 1275112
  Workaround for Neoverse N1 erratum 1262888
  Workaround for Neoverse N1 erratum 1262606
  Workaround for Neoverse N1 erratum 1257314
  Workaround for Neoverse N1 erratum 1220197
  Workaround for Neoverse N1 erratum 1207823
  Workaround for Neoverse N1 erratum 1165347
  Workaround for Neoverse N1 erratum 1130799
  Workaround for Neoverse N1 erratum 1073348
2019-07-04 06:58:51 +00:00
lauwal01 7d6f751867 Removing redundant ISB instructions
Replacing ISB instructions in each Errata workaround with a single ISB
instruction before the RET in the reset handler.

Change-Id: I08afabc5b98986a6fe81664cd13822b36cab786f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:17:22 -05:00
lauwal01 4d8801fe5a Workaround for Neoverse N1 erratum 1275112
Neoverse N1 erratum 1275112 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:17:19 -05:00
lauwal01 11c48370bd Workaround for Neoverse N1 erratum 1262888
Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:17:17 -05:00
lauwal01 411f4959b4 Workaround for Neoverse N1 erratum 1262606
Neoverse N1 erratum 1262606 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which delays instruction fetch after
branch misprediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:16:54 -05:00
lauwal01 335b3c79c7 Workaround for Neoverse N1 erratum 1257314
Neoverse N1 erratum 1257314 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR3_EL1 system register, which prevents parallel
execution of divide and square root instructions.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:16:32 -05:00
lauwal01 9eceb020d7 Workaround for Neoverse N1 erratum 1220197
Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:16:10 -05:00
lauwal01 ef5fa7d477 Workaround for Neoverse N1 erratum 1207823
Neoverse N1 erratum 1207823 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:15:48 -05:00
lauwal01 2017ab241c Workaround for Neoverse N1 erratum 1165347
Neoverse N1 erratum 1165347 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:15:15 -05:00
lauwal01 e34606f2e4 Workaround for Neoverse N1 erratum 1130799
Neoverse N1 erratum 1130799 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR2_EL1 system register.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:14:54 -05:00
lauwal01 a601afe158 Workaround for Neoverse N1 erratum 1073348
Neoverse N1 erratum 1073348 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUACTLR_EL1 system register, which disables static prediction.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02 09:13:31 -05:00
Girish Pathak 7e771a9bc4 tools/fiptool: Add Makefile.msvc to build on Windows.
This change adds nmake compatible Makefile.msvc file for
building (nmake /FMakefile.msvc) fiptool on the Windows.

Change-Id: Iccd1fe8da072edd09eb04b8622f27b3c4693b281
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
2019-07-02 14:12:01 +01:00
Sandrine Bailleux b01e0ad5cd Merge "zynqmp: add support for multi console interface" into integration 2019-07-02 09:58:51 +00:00
Soby Mathew 0d220b3519 Merge changes from topic "banned_api_list" into integration
* changes:
  Fix the License header template in imx_aipstz.c
  docs: Add the list of banned/use with caution APIs
2019-07-01 13:21:23 +00:00
Soby Mathew 2aca35fd9b Fix the License header template in imx_aipstz.c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af
2019-07-01 14:16:27 +01:00
Soby Mathew 140c8311f7 docs: Add the list of banned/use with caution APIs
Credit to sam.ellis@arm.com for the input to create the list.

Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-07-01 14:16:26 +01:00
Ambroise Vincent 55a08b35b1 zynqmp: add support for multi console interface
This patch addds multi console interface for ZynqMP
platform

Change-Id: I508a61412df2b71d04bca6a1139c8f32cbd7dccd
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2019-07-01 11:35:34 +05:30
Paul Beesley 39c92b6271 Merge changes from topic "av/console-port" into integration
* changes:
  qemu: use new console interface in aarch32
  warp7: remove old console from makefile
  Remove MULTI_CONSOLE_API flag and references to it
  Console: removed legacy console API
2019-06-28 11:04:02 +00:00
Ambroise Vincent e6ffc254a9 qemu: use new console interface in aarch32
Change-Id: Iab788e3e7cb2f83144255c4eb830712fd5cb6240
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-28 10:52:48 +01:00
Ambroise Vincent 0821731ac3 warp7: remove old console from makefile
Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-28 10:52:48 +01:00
Ambroise Vincent 5b6ebeec9c Remove MULTI_CONSOLE_API flag and references to it
The new API becomes the default one.

Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-28 10:52:48 +01:00
Paul Beesley e54b4dd9da Merge "Tegra: Fix typo in comment" into integration 2019-06-27 09:12:27 +00:00
Paul Beesley 8b95f81ce6 Merge "Tegra: Extend NS address check error output" into integration 2019-06-27 09:11:16 +00:00
Paul Beesley b4c99a9c5d Merge "n1sdp: add code for DDR ECC enablement and BL33 copy to DDR" into integration 2019-06-27 09:07:12 +00:00
Manoj Kumar de8bc83ee9 n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.

Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.

Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2019-06-26 14:07:51 +01:00
Paul Beesley 93c77622a6 Merge changes from topic "pull-out-drivers" into integration
* changes:
  intel: Add ncore ccu driver
  intel: Fix watchdog driver structure
  intel: Fix qspi driver write config
  intel: Pull out common drivers into platform common
2019-06-26 12:08:19 +00:00
Paul Beesley 5bf947ace0 Merge "rcar_gen3: drivers: pfc: E3: Replace REVERCED with REVERSED" into integration 2019-06-26 11:21:51 +00:00
Hadi Asyrafi 8a88a2271f intel: Add ncore ccu driver
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
2019-06-26 18:45:16 +08:00
Hadi Asyrafi 19e3644528 intel: Fix watchdog driver structure
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01
2019-06-26 18:45:16 +08:00
Hadi Asyrafi 2a16502339 intel: Fix qspi driver write config
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a
2019-06-26 18:45:16 +08:00
Hadi Asyrafi bf719f66a7 intel: Pull out common drivers into platform common
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa
2019-06-26 18:45:01 +08:00
Ambroise Vincent 51e24ec2c6 Console: removed legacy console API
This interface has been deprecated in favour of MULTI_CONSOLE_API.

Change-Id: I6170c1c8c74a890e5bd6d05396743fe62024a08a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-26 10:52:23 +01:00
Marek Vasut f361639127 rcar_gen3: drivers: pfc: E3: Replace REVERCED with REVERSED
Fix a typo, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id6abb4c192729f55b3500505860c7f7718944c62
2019-06-25 17:59:01 +02:00
Paul Beesley b26461e8a4 Merge changes Ie594b535,Ifa444dd5,Ie93e7fcc,I302cff20,I0f6c1cad, ... into integration
* changes:
  rcar_gen3: drivers: pfc: Move PFC drivers out of staging
  rcar_gen3: drivers: pfc: Checkpatch cleanup
  rcar_gen3: drivers: pfc: V3M: Fix camel case
  rcar_gen3: drivers: pfc: V3M: Drop forward declarations
  rcar_gen3: drivers: pfc: V3M: Switch to BIT() macro
  rcar_gen3: drivers: pfc: V3M: Checkpatch cleanup
  rcar_gen3: drivers: pfc: V3M: Switch to common register header file
  rcar_gen3: drivers: pfc: E3: Drop pfc_reg_write() forward declaration
  rcar_gen3: drivers: pfc: E3: Switch to BIT() macro
  rcar_gen3: drivers: pfc: E3: Checkpatch cleanup
  rcar_gen3: drivers: pfc: E3: Switch to common register header file
  rcar_gen3: drivers: pfc: D3: Switch to BIT() macro
  rcar_gen3: drivers: pfc: D3: Drop unused macros
  rcar_gen3: drivers: pfc: D3: Checkpatch cleanup
  rcar_gen3: drivers: pfc: D3: Switch to common register header file
  rcar_gen3: drivers: pfc: M3N: Drop forward declarations
  rcar_gen3: drivers: pfc: M3N: Switch to BIT() macro
  rcar_gen3: drivers: pfc: M3N: Checkpatch cleanup
  rcar_gen3: drivers: pfc: M3N: Switch to common register header file
  rcar_gen3: drivers: pfc: M3W: Fix camel case
  rcar_gen3: drivers: pfc: M3W: Drop forward declarations
  rcar_gen3: drivers: pfc: M3W: Switch to BIT() macro
  rcar_gen3: drivers: pfc: M3W: Checkpatch cleanup
  rcar_gen3: drivers: pfc: M3W: Switch to common register header file
  rcar_gen3: drivers: pfc: H3: Drop pfc_reg_write() forward declaration
  rcar_gen3: drivers: pfc: H3: Switch to BIT() macro
  rcar_gen3: drivers: pfc: H3: Drop unused macros
  rcar_gen3: drivers: pfc: H3: Checkpatch cleanup
  rcar_gen3: drivers: pfc: H3: Switch to common register header file
  rcar_gen3: drivers: pfc: Introduce common register header file
  rcar_gen3: drivers: pfc: D3: Drop unused M3W check
2019-06-25 13:49:15 +00:00
John Tsichritzis 1b779c8c49 Merge "doc: Fix typo in file interrupt-framework-design.rst" into integration 2019-06-25 11:33:52 +00:00
John Tsichritzis e9e74aa4c8 Merge "Fix links in documentation" into integration 2019-06-25 09:52:16 +00:00
John Tsichritzis 2645fceb50 Fix links in documentation
Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-06-24 13:22:30 +01:00