Commit Graph

8705 Commits

Author SHA1 Message Date
Pankaj Gupta b53334dac4 nxp: adding gic apis for nxp soc
GIC api used by NXP SoC is based on:
- arm provided drivers: /drivers/arm/gic

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: If3d470256e5bd078614f191e56062c4fbd97f8bd
2021-03-24 09:49:31 +05:30
Pankaj Gupta e3e48b5c38 nxp: gpio driver support
NXP General Purpose Input/Output driver support for
NXP platforms.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a3574f1d5d12e4a65ff60f640d4e77e2defd6d4
2021-03-24 09:49:31 +05:30
Pankaj Gupta 34412eda32 nxp: added csu driver
NXP Central Security Unit(CSU) for NXP SoC.
CSU is used for:
- Access permissions for peripheral that donot have their own
  access control.
- Locking of individual CSU settings until the next POR
- General purpose security related control bits

Refer NXP SoC manuals fro more details.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I07a4729c79c5e2597f8b2a782e87e09f7f30c2ca
2021-03-24 09:49:31 +05:30
Pankaj Gupta d57186ea2c nxp: driver pmu for nxp soc
Driver for NXP IP for Power Management Unit.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I855657eddab357cb182419b188ed8861c46a1b19
2021-03-24 09:49:31 +05:30
Pankaj Gupta b35ce0c413 nxp: ddr driver enablement for nxp layerscape soc
DDR driver for NXP layerscape SoC(s):
 - lx2160aqds
 - lx2162aqds
 - lx2160ardb
 - Other Board with SoC(s) like ls1046a, ls1043a etc;
	-- These other boards are not verified yet.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
2021-03-24 09:49:31 +05:30
Pankaj Gupta c6d9fdbc78 nxp: i2c driver support.
NXP I2C driver support for NXP SoC(s).

Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I234b76f9fa1b30dd13aa087001411370cc6c8dd0
2021-03-24 09:49:31 +05:30
Pankaj Gupta d8e9799921 NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored
- current security state of the SoC.
- Tamper detect etc.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8ff809fe2f3fd013844ab3d4a8733f53c2b06c81
2021-03-24 09:49:31 +05:30
Pankaj Gupta 3979c6d924 NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
  different platform keys etc.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c
2021-03-24 09:49:31 +05:30
Pankaj Gupta 76f735fd82 NXP: Interconnect API based on ARM CCN-CCI driver
CCN API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCN driver
- driver/arm/ccn

CCI API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCI driver
- driver/arm/cci

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I7682c4c9bd42f63542b3ffd3cb6c5d2effe4ae0a
2021-03-24 09:49:31 +05:30
Pankaj Gupta de0b101248 NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on:
- drivers/arm/tzc

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I524433ff9fafe1170b13e99b7de01fe957b6d305
2021-03-24 09:49:31 +05:30
Pankaj Gupta 447a42e735 NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
2021-03-24 09:49:31 +05:30
Pankaj Gupta 86b1b89fbf nxp: add dcfg driver
NXP SoC needs Device Configuration driver to
fetch the current SoC configuration.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ie17cca01a8eb9a6f5feebb093756f577692432bf
2021-03-24 09:49:31 +05:30
Pankaj Gupta 0499215e1d nxp:add console driver for nxp platform
NXP SoCs, supports two types of UART controller:
- PL011 - using ARM drivers sources
- 16550 - using TI drivers source

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Iacbcefd2b6e5d96f83fa00ad25b4f63a4c822bb4
2021-03-24 09:49:31 +05:30
Pankaj Gupta 3527d6d21d tools: add mechanism to allow platform specific image UUID
Generic framework is added to include platform defined UUID.

This framework is added for the following:
- All NXP SoC based platforms needed additional fip-fuse.bin
- NXP SoC lx2160a based platforms requires additional fip-ddr.bin

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ibe05d9c596256e34077287a490dfcd5b731ef2cf
2021-03-24 09:49:31 +05:30
Pankaj Gupta 18644159a6 tbbr-cot: conditional definition for the macro
Conditional definition for the macro MAX_NUMBER_IDS.

This will allow to update this definition by the platform
specific implementation.

Since, NXP SoC lx2160a based platforms requires additional
FIP DDR to be loaded before initializing the DDR.

It requires addition of defines for DDR image IDs.
A dedicated header plat_tbbr_img_def.h is added to the platform
folder - plat/nxp/common/include/default/

Inclusion of this header file will depend on the compile time
flag PLAT_TBBR_IMG_DEF.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I4faba74dce578e2a34acbc8915ff75d7b8368cee
2021-03-24 09:49:31 +05:30
Pankaj Gupta ff67fca5ac tbbr-cot: fix the issue of compiling time define
Incorrect value is picked for TF_MBEDTLS_USE_RSA defination,
even if the TF_MBEDTLS_RSA is enabled.

Due to which PK_DER_LEN is defined incorrectly.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2ca4ca121e0287b88ea689c885ddcd45a34a3e91
2021-03-24 09:49:31 +05:30
Pankaj Gupta b94bf967e6 cert_create: updated tool for platform defined certs, keys & extensions
Changes to 'tools/cert_create' folder, to include platform defined
certificates, keys, and extensions.

NXP SoC lx2160a : based platforms requires additional
FIP DDR to be loaded before initializing the DDR.

To enable chain of trust on these platforms, FIP DDR
image needs to be authenticated, additionally.

Platform specific folder 'tools/nxp/cert_create_helper'
is added to support platform specific macros and definitions.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I4752a30a9ff3aa1d403e9babe3a07ba0e6b2bf8f
2021-03-24 09:49:31 +05:30
Pankaj Gupta 6c74c9977d tbbr-tools: enable override TRUSTED_KEY_CERT
Platforms, which requires additional images to be
verified using TBBR; such that their key certificate
is tied to TRUSTED_KEY_CERT.

For such platforms, if make commands runs twice:
 - Once with targets as bl2 & fip.bin, and
 - Again to build the target as the additional image.

then, if path to the TRUSTED_KEY_CERT varies in the
makefile with make-target of the additional image, then
there would be two location where "trusted_key.crt" will
be created.

This patch helps overriding the TRUSTED_KEY_CERT from any .mk
in the platform's makefile structure.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I775a2c409035504b21b0bbe5a4f9046898163eed
2021-03-24 09:49:31 +05:30
Samuel Holland de37db6c59 allwinner: Use CPUIDLE hardware when available
This works even on SoCs that do not have an ARISC, and it avoids
clobbering whatever ARISC firmware might be running.

Change-Id: I9f2fed597189bb387de79e8e76a7da3375e1ee91
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-23 23:46:01 +00:00
André Przywara 4a81a9f1be Merge "fdt: Use proper #address-cells and #size-cells for reserved-memory" into integration 2021-03-23 18:09:07 +01:00
Andre Przywara 81146c46f6 fdt: Use proper #address-cells and #size-cells for reserved-memory
The devicetree binding document[1] for the /reserved-memory node demands
that the number of address and size-cells in the reserved-memory node
must match those values in the root node. So far we were forcing a
64-bit address along with a 32-bit size.

Adjust the code to query the cells values from the root node, and
populate the newly created /reserved-memory node accordingly.

This fixes the fdt_add_reserved_memory() function when called on a
devicetree which does not use the 2/1 pair. Linux is picky about this
and will bail out the parsing routine, effectively ignoring the
reserved-memory node:
[    0.000000] OF: fdt: Reserved memory: unsupported node format, ignoring

[1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
    in the Linux kernel source tree

Change-Id: Ie126ebab4f3fedd48e12c9ed4bd8fa123acc86d3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-23 18:08:45 +01:00
Ying-Chun Liu (PaulLiu) e364a8c367 plat: imx8mm: Add image load logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I0557ce6d0aa5ab321cac1ee25280b96762024396
2021-03-23 21:29:32 +08:00
Ying-Chun Liu (PaulLiu) 37ac9b7f11 plat: imx8mm: Add initial defintions to facilitate FIP layout
Adds a number of definitions consistent with the established WaRP7
equivalents specifying number of io_handles and block devices.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3
2021-03-23 21:29:32 +08:00
Ying-Chun Liu (PaulLiu) ee4d094acf plat: imx8mm: Add image io-storage logic for TBBR FIP booting
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I9833a54d0938d70886ac88b1922b17edf1dee8e0
2021-03-23 21:29:32 +08:00
Ying-Chun Liu (PaulLiu) 1329f9647c plat: imx8mm: Add imx8mm_private.h to the build
Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I8523f1370312ed22ff7ca710cd916be52f725e3c
2021-03-23 21:29:32 +08:00
Yann Gautier 236fc428bb stm32mp1: add TZC400 interrupt management
TZC400 is configured to raise an interrupt in case of faulty access.
Call the new added tzc400_it_handler, in case this interrupt occurs.

Change-Id: Iaf4fa408a8eff99498042e11e2d6177bad39868c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-03-23 13:06:15 +01:00
Yann Gautier 1e80c49810 stm32mp1: use TZC400 macro to describe filters
On STM32MP15, only filters 0 and 1 are used.
Use TZC_400_REGION_ATTR_FILTER_BIT() macro for those 2 filters 0 and 1
instead of U(3).

Change-Id: Ibc61823842ade680f59d5b66b8db59b6a30080e4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-03-23 13:06:15 +01:00
Yann Gautier 34c1a1a43c tzc400: add support for interrupts
A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is enabled, more information about the faulty access
(address, NSAID, type of access) is displayed.

Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-03-23 13:06:15 +01:00
Olivier Deprez 9e28b85444 Merge "SPM: Fix error codes size in SPMD handler" into integration 2021-03-23 08:47:58 +01:00
Jan Kiszka 830c7657d5 rpi4: Switch to gicv2.mk and GICV2_SOURCES
Addresses the deprecation warning produced by
drivers/arm/gic/common/gic_common.c.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I1a3ff4835d0f94c74b405db10622e99875ded82b
2021-03-22 20:46:25 +01:00
Madhukar Pappireddy e84ca57130 Merge "plat: xilinx: versal: Mark IPI calls secure/non-secure" into integration 2021-03-19 17:24:58 +01:00
Tejas Patel 4697164a3f plat: xilinx: versal: Mark IPI calls secure/non-secure
BIT24 of IPI command header is used to determine if caller is
secure or non-secure.

Mark BIT24 of IPI command header as non-secure if SMC caller
is non-secure.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iec25af8f4b202093f58e858ee47cd9cd46890267
2021-03-19 07:47:12 -07:00
J-Alves e46b2fd210 SPM: Fix error codes size in SPMD handler
FF-A specification states that error codes should be typed int32_t.
SPMD's uses uint64_t for return values, which if assigned with a signed
type would have sign extension, and change the size of the return from
32-bit to 64-bit.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I288ab2ffec8330a2fe1f21df14e22c34bd83ced3
2021-03-19 15:07:46 +01:00
Roman Beranek 9655a1f54b
plat/allwinner: do not setup 'disabled' regulators
If a PMIC regulator has its DT node disabled, leave the regulator off.

Change-Id: I895f740328e8f11d485829c3a89a9b9f8e5644be
Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
2021-03-19 12:57:50 +01:00
Madhukar Pappireddy 2e0e51f425 Merge "Bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled" into integration 2021-03-18 21:26:57 +01:00
Madhukar Pappireddy cab2b183be Merge "tools_share/uuid: Add EFI_GUID representation" into integration 2021-03-18 16:56:51 +01:00
Madhukar Pappireddy 0888fcf252 Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration 2021-03-18 15:15:11 +01:00
Madhukar Pappireddy 51bb1d7361 Bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled
Typically, interrupts for a specific security state get handled in the
same security execption level if the execution is in the same security
state. For example, if a non-secure interrupt gets fired when CPU is
executing in NS-EL2 it gets handled in the non-secure world.

However, interrupts belonging to the opposite security state typically
demand a world(context) switch. This is inline with the security
principle which states a secure interrupt has to be handled in the
secure world. Hence, the TSPD in EL3 expects the context(handle) for a
secure interrupt to be non-secure and vice versa.

The function "tspd_sel1_interrupt_handler" is the handler registered
for S-EL1 interrupts by the TSPD. Based on the above assumption, it
provides an assertion to validate if the interrupt originated from
non-secure world and upon success arranges entry into the TSP at
'tsp_sel1_intr_entry' for handling the interrupt.

However, a race condition between non-secure and secure interrupts can
lead to a scenario where the above assumptions do not hold true and
further leading to following assert fail.

This patch fixes the bug which causes this assert fail:

	ASSERT: services/spd/tspd/tspd_main.c:105
	BACKTRACE: START: assert
	0: EL3: 0x400c128
	1: EL3: 0x400faf8
	2: EL3: 0x40099a4
	3: EL3: 0x4010d54
	BACKTRACE: END: assert

Change-Id: I359d30fb5dbb1429a4a3c3fff37fdc64c07e9414
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-03-18 08:38:23 -05:00
Madhukar Pappireddy 0fb7363899 Merge "plat: xilinx: Add timeout while waiting for IPI Ack" into integration 2021-03-18 14:15:48 +01:00
Tomas Pilar e831923f95 tools_share/uuid: Add EFI_GUID representation
The UEFI specification details the represenatation
for the EFI_GUID type. Add this representation to the
uuid_helper_t union type so that GUID definitions
can be shared verbatim between UEFI and TF-A header
files.

Change-Id: Ie44ac141f70dd0025e186581d26dce1c1c29fce6
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
2021-03-18 14:14:22 +01:00
Madhukar Pappireddy 706058c255 Merge "mmc:prevent accessing to the released space in case of wrong usage" into integration 2021-03-18 14:11:20 +01:00
Chris Kay 4e04478aac arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms
The speculation barrier feature (`FEAT_SB`) was introduced with and
made mandatory in the Armv8.5-A extension. It was retroactively made
optional in prior extensions, but the checks in our code-base do not
reflect that, assuming that it is only available in Armv8.5-A or later.

This change introduces the `ENABLE_FEAT_SB` definition, which derives
support for the `sb` instruction in the assembler from the feature
flags passed to it. Note that we assume that if this feature is enabled
then all the cores in the system support it - enabling speculation
barriers for only a subset of the cores is unsupported.

Signed-off-by: Chris Kay <chris.kay@arm.com>
Change-Id: I978ed38829385b221b10ba56d49b78f4756e20ea
2021-03-18 12:34:34 +01:00
Sandrine Bailleux e3ff1766e3 Merge "tzc400: correct FAIL_CONTROL Privileged bit" into integration 2021-03-17 13:51:11 +01:00
deqi.hu 13f3c5166f mmc:prevent accessing to the released space in case of wrong usage
1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
  In order to avoid referencing the released space on the stack when maybe MISUSED,
  it`s better to use global variables to store mmc_device_info in mmc.c
2.Delete redundant;

Signed-off-by: deqi.hu@siengine.com
Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
2021-03-17 11:04:21 +01:00
Olivier Deprez ae030052a1 Merge changes from topic "od/ffa_spmc_pwr" into integration
* changes:
  SPM: declare third cactus instance as UP SP
  SPMD: lock the g_spmd_pm structure
  FF-A: implement FFA_SECONDARY_EP_REGISTER
2021-03-16 16:15:03 +01:00
Michal Simek 4a7b060b3d plat: xilinx: versal: Remove cortex-a53 compilation
Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6
2021-03-16 13:17:37 +01:00
Madhukar Pappireddy 332649da47 Merge changes from topic "matterhorn_elp" into integration
* changes:
  plat: tc0: add matterhorn_elp_arm library to tc0
  cpus: add Matterhorn ELP ARM cpu library
2021-03-15 17:50:08 +01:00
Olivier Deprez e96fc8e7d6 SPM: declare third cactus instance as UP SP
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU
instantiated in a Secure Partition:
-A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs.
An EC is pinned to a corresponding physical CPU.
-An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to
the physical CPU from which the FF-A call is originating.
This change permits exercising the latter case within the TF-A-tests
framework.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
2021-03-15 12:29:19 +01:00
Olivier Deprez 473ced5670 SPMD: lock the g_spmd_pm structure
Add a lock and spin lock/unlock calls when accessing the fields of the
SPMD PM structure.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9bab705564dc1ba003c29512b1f9be5f126fbb0d
2021-03-15 12:29:19 +01:00
Olivier Deprez cdb49d475e FF-A: implement FFA_SECONDARY_EP_REGISTER
Remove the former impdef SPMD service for SPMC entry point
registration. Replace with FFA_SECONDARY_EP_REGISTER ABI
providing a single entry point address into the SPMC for
primary and secondary cold boot.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I067adeec25fc12cdae90c15a616903b4ac4d4d83
2021-03-15 12:29:11 +01:00