Commit Graph

708 Commits

Author SHA1 Message Date
Soby Mathew 42cdeb9308 Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration 2019-09-13 12:09:21 +00:00
Justin Chadwell 6a415a508e Remove RSA PKCS#1 v1.5 support from cert_tool
Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in that form. This patch fully removes the ability for
cert_tool to generate these certificates.

Additionally, this patch also fixes a bug where the issuing certificate
was a RSA and the issued certificate was EcDSA. In this case, the issued
certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per
PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now
that PKCS#1 v1.5 support is removed, all certificates that are signed
with RSA now use the more modern padding scheme.

Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-09-12 15:27:41 +01:00
Justin Chadwell aacff7498c Support larger RSA key sizes when using MBEDTLS
Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations with the larger, higher-precision numbers required. With
these changes to the arguments passed to MBEDTLS, TF-A now supports
using 3072 (3K) and 4096 (4K) keys in certificates.

Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-09-12 15:27:39 +01:00
Soby Mathew f38e5182f7 Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration
* changes:
  rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: qos: update QoS setting
  rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
  rcar_gen3: drivers: ddr_b: Fix line-over-80s
  rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
  rcar_gen3: drivers: ddr_b: Clean up camel case
  rcar_get3: drivers: ddr_b: Basic checkpatch fixes
  rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
  rcar_get3: drivers: ddr: Clean up common code
2019-09-12 11:11:34 +00:00
Soby Mathew 9af73b3688 Merge changes from topic "amlogic-refactoring" into integration
* changes:
  amlogic: Fix includes order
  amlogic: Fix header guards
  amlogic: Fix prefixes in the SoC specific files
  amlogic: Fix prefixes in the PM code
  amlogic: Fix prefixes in the SCPI related code
  amlogic: Fix prefixes in the MHU code
  amlogic: Fix prefixes in the SIP/SVC code
  amlogic: Fix prefixes in the thermal driver
  amlogic: Fix prefixes in the private header file
  amlogic: Fix prefixes in the efuse driver
  amlogic: Fix prefixes in the platform macros file
  amlogic: Fix prefixes in the helpers file
  amlogic: Rework Makefiles
  amlogic: Move the SIP SVC code to common directory
  amlogic: Move topology file to common directory
  amlogic: Move thermal code to common directory
  amlogic: Move MHU code to common directory
  amlogic: Move efuse code to common directory
  amlogic: Move platform macros assembly file to common directory
  amlogic: Introduce unified private header file
  amlogic: Move SCPI code to common directory
  amlogic: Move the SHA256 DMA driver to common directory
  amlogic: Move assembly helpers to common directory
  amlogic: Introduce directory parameters in the makefiles
  meson: Rename platform directory to amlogic
2019-09-12 10:58:43 +00:00
Yann Gautier ebf851ed34 stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver
The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CRLF.
Remove the code in driver, and add the flag for STM32MP1.

Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-10 17:21:58 +02:00
Carlo Caione 01b2a7fc32 amlogic: Move the SHA256 DMA driver to common directory
The SHA256 DMA driver can be used by multiple SoCs. Move it to the
common directory.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5
2019-09-05 10:39:30 +01:00
Carlo Caione 4a079c752b meson: Rename platform directory to amlogic
Meson is the internal code name for the SoC family. The correct name for
the platform should be Amlogic. Change the name of the platform
directory.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
2019-09-05 10:39:25 +01:00
Yann Gautier d9d803e0be mmc: stm32_sdmmc2: correctly manage block size
DBLOCKSIZE should be filled such as the data size is 2^DBLOCKSIZE.
Hence it is calculated with __builtin_ctz.

Change-Id: Id6b5ff9b594afc4fc523a388011beed307e6abd1
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-02 17:53:16 +02:00
Yann Gautier 2c2c9f1eb1 mmc: stm32_sdmmc2: manage max-frequency property from DT
If the max-frequency property is provided in the device tree mmc node,
it should be managed. The max allowed frequency will be the min between
this property value and what the card can support.

Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-02 17:53:14 +02:00
Yann Gautier 1e91952942 stm32mp1: move check_header() to common code
This function can be used on several stm32mp devices, it is then moved in
plat/st/common/stm32mp_common.c.

Change-Id: I862debe39604410f71a9ddc28713026362e9ecda
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-02 17:52:55 +02:00
Yann Gautier 4b549b2153 stm32mp1: add support for LpDDR3
This change enables LpDDR3 initialization with PMIC.

Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-02 17:52:29 +02:00
Yann Gautier e463d3f43e stm32mp1: use a common function to check spinlock is available
To use spinlocks, MMU should be enabled, as well as data cache.
A common function is created (moved from clock file).
It is then used whenever a spinlock has to be taken, in BSEC and clock
drivers.

Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-09-02 17:51:57 +02:00
Yann Gautier 6cb45f8984 clk: stm32mp: enable RTCAPB clock for dual-core chips
In order to correctly manage the bring-up of non boot CPUs, the RTCAPB
clock needs to be enabled.
It controls the access to backup registers, where the CPU entrypoint
will be stored.

Change-Id: Ifeeceb4faf64bc9e0778030444f437cc0bb27272
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2019-09-02 17:51:30 +02:00
Yann Gautier 73680c230f stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.

The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.

An increase of BL2 size is also required when adding this new code.

Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
2019-09-02 17:25:08 +02:00
Chiaki Fujii fbee88fbb0 rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.37.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I072c0f61cd896e74e4e1eee39d313f82cf2f7295
2019-08-29 13:02:30 +02:00
Yoshifumi Hosoya bf881832e8 rcar_gen3: drivers: qos: update QoS setting
[IPL/QoS]
- Update M3 Ver.3.0 QoS setting rev.0.04.

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I798401f417df6a352d94311ea07a1e96ba562f6a
2019-08-29 13:02:30 +02:00
Marek Vasut f3f5aba6e8 rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers
Clean up the DDR B header files and remove checkpatch errors.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9648ef5511df299688fd5284513812d32a1f8064
2019-08-29 13:02:30 +02:00
Marek Vasut 4ca57bae27 rcar_gen3: drivers: ddr_b: Fix line-over-80s
Fix as many line-over-80s as possible. There are still a few remaining,
which would need further refactoring.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7225d9fab658d05e3315d8c3fa3c9f3bbb1ab40d
2019-08-29 13:02:30 +02:00
Marek Vasut 087561475e rcar_gen3: drivers: ddr_b: Further checkpatch cleanups
Address more checkpatch CHECKs and ERRORs, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ife682288cef3afa860571b2aca647c9ffe936125
2019-08-29 13:02:30 +02:00
Marek Vasut fcd81d6f93 rcar_gen3: drivers: ddr_b: Clean up camel case
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e
2019-08-29 13:02:30 +02:00
Marek Vasut a8497fdb72 rcar_get3: drivers: ddr_b: Basic checkpatch fixes
Do basic automated checkpatch fixes on the ddr_b, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie401ec049a05d2c4c8044749994391adea171679
2019-08-29 13:02:30 +02:00
Marek Vasut f12039be95 rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
The ddr_a and ddr_b register macros are the same for the most part,
unify them into a single header.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75
2019-08-29 13:02:30 +02:00
Marek Vasut 40c711a360 rcar_get3: drivers: ddr: Clean up common code
Do minor coding style changes to the common DDR init code to make it
checkpatch compliant and move macros out into rcar_def.h.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
2019-08-29 13:02:30 +02:00
Paul Beesley 7cc287dea6 Merge "rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*" into integration 2019-08-20 14:14:03 +00:00
Paul Beesley 44f4bb24ff Merge "rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h" into integration 2019-08-20 14:12:40 +00:00
Masahiro Yamada f51df47572 console: add a flag to prepend '\r' in the multi-console framework
Currently, console drivers prepend '\r' to '\n' by themselves. This is
common enough to be supported in the framework.

Add a new flag, CONSOLE_FLAG_TRANSLATE_CRLF. A driver can set this
flag to ask the framework to transform LF into CRLF instead of doing
it by itself.

Change-Id: I4f5c5887591bc0a8749a105abe62b6562eaf503b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-08-19 17:00:08 +09:00
Marek Vasut df51d8fe7e rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate
RCAR_PRODUCT_* macro.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96
2019-08-16 15:15:12 +02:00
Marek Vasut 7c103d608d rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h
Pull out the PRR_* macros into rcar_def.h and remove multiple copies of
it. Now that there are still RCAR_* macros in rcar_def.h too and they
have the exact same meaning as the PRR_* macros, but that's for another
patch.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc
2019-08-16 15:13:23 +02:00
Julius Werner 402b3cf876 Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:45:03 -07:00
Julius Werner d5dfdeb65f Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-08-01 13:14:12 -07:00
Gilad Ben-Yossef 76f3c7dc8b cryptocell: add product version awareness support
Add support for multiple Cryptocell revisions which
use different APIs.

This commit only refactors the existing code in preperation to the addition
of another Cryptocell revisions later on.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I16d80b31afb6edd56dc645fee5ea619cc74f09b6
2019-07-25 13:38:07 +03:00
Gilad Ben-Yossef 36ec2bb0bc cryptocell: move Cryptocell specific API into driver
Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
  copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
  API and products.

Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e
2019-07-25 13:29:15 +03:00
Soby Mathew df5bd3bf9e Merge "console: update skeleton" into integration 2019-07-17 08:51:27 +00:00
Soby Mathew 7cdd55af62 Merge changes I68941876,Ib7961812,I758661d3,I4f3e3812,I9b26b838, ... into integration
* changes:
  rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
  rcar_gen3: drivers: ddr-a: Pass ddrBackup around
  rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h
  rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style
  rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style
  rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32()
  rcar_gen3: drivers: ddr-a: Unify register definitions
2019-07-17 08:51:10 +00:00
Soby Mathew f7694165c7 Merge "rcar_gen3: drivers: ddr: Replace BITn with BIT(n) macro" into integration 2019-07-17 08:50:58 +00:00
Ambroise Vincent 52e91081a9 console: update skeleton
Update the skeleton implementation of the console interface.

The 32 bit version was outdated and has been copied from the 64 bit
version.

Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-07-16 13:01:02 +00:00
Soby Mathew d0d0f17164 Merge changes from topic "jc/shift-overflow" into integration
* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour
2019-07-16 10:11:27 +00:00
Marek Vasut c85f8f0965 rcar_gen3: drivers: ddr-a: Fix E3 DDR init coding style
Coding style cleanup, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I689418768e87a8c1b6eeeb9f1a48dfb333908017
2019-07-15 06:15:48 +02:00
Marek Vasut 2c400e9492 rcar_gen3: drivers: ddr-a: Pass ddrBackup around
Pass the ddrBackup variable around instead of making it a global variable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib796181247712e464b77f5f8be5f851745727d74
---
NOTE: The camelcase is fixed in later patch.
2019-07-14 12:15:46 +02:00
Marek Vasut 32e6b50ed5 rcar_gen3: drivers: ddr-a: Inline ddr_init_e3.h
Partly inline ddr_init_e3.h into ddr_init_e3.c . Drop duplicate
INITDRAM_* macros, which are defined in boot_init_dram.h .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I758661d337a86b6a07f82cd4067fbc149cbaed1e
2019-07-14 12:15:46 +02:00
Marek Vasut 8bfca58bbf rcar_gen3: drivers: ddr-a: Fix V3M DDR init coding style
Coding style cleanup, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4f3e3812ffaa24fec50857756539b563eff33cdd
2019-07-14 12:15:43 +02:00
Marek Vasut d2ee6e01d0 rcar_gen3: drivers: ddr-a: Fix D3 DDR init coding style
Coding style cleanup, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9b26b838e8c45d9b4f53c67663ec94002dd9edfe
2019-07-14 11:09:31 +02:00
Marek Vasut dfd80943d5 rcar_gen3: drivers: ddr-a: Replace {Read,Write}Reg_32() with mmio_{read,write}_32()
Replace ad-hoc register accessors with generic ones, remove the ad-hoc
implementation. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I21446a00a38c6a39d6a48652c34f59814074e831
2019-07-14 09:25:01 +02:00
Marek Vasut efe6eaabe1 rcar_gen3: drivers: ddr-a: Unify register definitions
Unify boot_init_dram_regdef_*.h into boot_init_dram_regdef.h and
clean up it's coding style a bit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Iae3375969c05f80209ebf7b1ebc3633a7f6317ff
2019-07-14 09:25:00 +02:00
Marek Vasut 8ddd91b0f6 rcar_gen3: drivers: ddr: Replace BITn with BIT(n) macro
Remove the ad-hoc BITn macros and replace them with generic BIT(n) macro.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I5d0b44d6cba5a69895fed505f6ff780d3574907f
2019-07-14 09:16:35 +02:00
Toshiyuki Ogasahara c186ec5139 rcar_gen3: drivers: rpc: Modify PFC code
Modify PFC code and rename macro of MFIS according to Errata of
Hardware User's Manual

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0ece522647319286350843bbbe8b8ba8b0ae9bac
2019-07-12 12:11:38 +02:00
Toshiyuki Ogasahara a3aa877c9e rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
Modify RPC code according to Errata of Hardware User's Manual

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I82d0a2136c7f18870842f84c49343977708eef1e
2019-07-12 12:11:38 +02:00
Chiaki Fujii 783c5304b2 rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.36.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia4fc9456876a14a9cf3ced93163477974f6cc8bf
2019-07-12 12:11:37 +02:00
Justin Chadwell 9264f0876e Update synopsys drivers to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I54560fe290e7dc52d364d0fe1c81a16f4c8d9a7b
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-07-12 09:12:19 +01:00