This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html
Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.
The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.
msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.
This change ensures we capture the x field, which we are interested in and
not the f field which we are not.
Fixes: f3b4914be3 ('AArch32: Add generic changes in BL1')
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].
This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0]
fields of the SPSR. For the purposes of initial setup of the SPSR the x and
c fields should be sufficient and importantly will capture the necessary
lower-order control bits that f:c alone do not.
This is important to do to ensure the SPSR is set to the mode the platform
intends prior to performing an eret.
Fixes: b1d27b484f ("bl2-el3: Add BL2_EL3 image")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is 14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators
this patch add the basic support for i.MX8MM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
The security advisories would all appear on a single line. Use bullet
points instead to improve the readability.
Change-Id: Id631985d7d559b3632f43d695cffa6735520b64a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
The comment suggests checking version numbers and
a checksum but there doesn't seem to be any usable
data for either of these.
For example, fip_toc_header_t doesn't contain any
version information and neither does fip_toc_entry_t.
As the function name "is_valid_header" suggests, this
function is not concerned with checksumming any of
the table of contents entries.
Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
It is quite unlikely that this number will ever change and, if it
does need to change, we should have a good reason to do so. It
seems that this comment is now redundant.
Change-Id: I409c764080748e338e9bc5606bbdcc475213fb6e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
for the i.MX8M SOCs, part of the code for gpc
and PSCI implementation can be reused and make it
common for all these SoCs. this patch extracts
the common part for reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image initialises its context. This is done to ensure that the
image environment is initialised in a safe state, regardless of the
reset value of the bit.
Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is
now handled in the dw_prepare function
- after the CMD completes, when doing dw_read, we need to invalidate cache
and wait for the data transfer to complete
- Need to set FIFO threshold, otherwise DMA might never get the interrupt
to read or write
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Some checks are ignored as they do not match TF-A coding rules:
PREFER_KERNEL_TYPES, USLEEP_RANGE
or MISRA:
COMPARISON_TO_NULL, UNNECESSARY_PARENTHESES
Change-Id: I335ede89fc872a6169028552d1ba9312fc61a0ba
Signed-off-by: Yann Gautier <yann.gautier@st.com>
It can be handy for example to add --strict option which can detect more
coding issues, even if not mandated by TF-A coding rules.
To use it:
CHECKPATCH_OPTS="--strict" make checkpatch
Change-Id: I707e4cc2d1250b21f18ff16169b5f1e5ab03a7ed
Signed-off-by: Yann Gautier <yann.gautier@st.com>
MISRA C:2012 Rule 15.6 asks to have braces for the body of an if,
for, or while statement.
This conflicts with checkpatch, and the warning should then be ignored.
Change-Id: I22589b68b03f19a426d3bcbc10a99d4e4c76eced
Signed-off-by: Yann Gautier <yann.gautier@st.com>
This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status and secure-status, as these OTPs are accessible
by secure and non-secure world.
The stgen node is also moved to this file.
Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad
Signed-off-by: Yann Gautier <yann.gautier@st.com>
So far the DT node describing the AXP803 PMIC used in many Allwinner A64
boards had only one subnode, so our code just entering the first subnode
to find all regulators worked fine.
However recent DT updates in the Linux kernel add more subnodes *before*
that, so we need to make sure to explicitly enter the "regulators"
subnode to find the information we are after.
Improve some DT node parsing error handling on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.
Adapt to use r8 and adapt the comment about registers allowed
to clober.
I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.
Fixes: a6f340fe58 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Allow EL2 (e.g. U-Boot) to load the configuration object at runtime
into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot
and U-Boot SPL with PMU FW without hard-coding the configuration
object.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges
3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field.
Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Soby Mathew
Ambroise Vincent
Dimitris Papastamos
Bryan O'Donoghue
Muhammad Hadi Asyrafi Abdul Halim
Jacky Bai
Masahisa Kojima
Alexei Fedorov
Louis Mayencourt
Sandrine Bailleux
Paul Beesley
John Tsichritzis
Tien Hock, Loh
Yann Gautier
Andre Przywara
Heiko Stuebner
Luca Ceresoli