Commit Graph

4887 Commits

Author SHA1 Message Date
Yann Gautier ff7675ebf9 fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.

Change-Id: Iaca959add924e0e1fa2e56fab2348f0ee36e5fa7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-17 09:53:04 +01:00
Madhukar Pappireddy 7468be1274 Merge changes from topic "fconf_get_index" into integration
* changes:
  feat(stm32mp1): skip TOS_FW_CONFIG if not in FIP
  feat(fconf): add a helper to get image index
2021-12-14 20:58:09 +01:00
Yann Gautier acf28c267b feat(st): protect UART during platform init
Protect the UART instance used for serial boot
with UART used for console.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ieee1557b34e7baa81594c3fbf0513191737027bf
2021-12-14 11:34:16 +01:00
Yann Gautier aafff04354 feat(stm32mp1): update console management for SP_min
Use stm32mp_uart_console_setup() in SP_min setup.
Adapt the function stm32mp_uart_console_setup() for BL32 (no reset, add
CONSOLE_FLAG_RUNTIME under DEBUG.

Change-Id: Ib2d35c8d285dafb680aa218872ad679cbf43d0ed
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier 86240942fa refactor(stm32mp1): improve console management in BL2
Use newly created function stm32mp_uart_console_setup().
And remove now useless code.

Change-Id: Ib8d0319d3f4f54309848bc225b58608cea73bad9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier 53612f7293 feat(plat/st): add a function to configure console
To ease console configuration, a dedicated function is created:
stm32mp_uart_console_setup(). The code will also be common for the
different BLs.

Change-Id: Idf3cad756f125ca2313cf30b1311637a9df8f27f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier a6bfa75cf2 feat(stm32mp1): add stm32_get_boot_interface function
Add function stm32_get_boot_interface to get the current boot interface
from information saved in the TAMP register.

Change-Id: I23af43c68eeaebe4c45920a57d739117aea3fbb1
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier 4dc77a35e3 refactor(stm32mp1): move stm32_save_boot_interface()
The function stm32_save_boot_interface()is moved to stm32mp1_private.c
file. The files stm32mp1_context.{c,h} are removed.
As return is always 0, change the function to return void.
Call it earlier, to be able to use it when configuring console.

Change-Id: I8986e1257dc8e8708eab044a51ea1f2426b16597
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier d7176f0319 fix(stm32mp1): deconfigure UART RX pins
Those pins are configured by ROM code, for serial boot use cases.
Their configs are reset if the boot is done on UART, but not on USB.
This should then be done in TF-A. This has to be done after clock
init, and before console is configured.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I29a9694e25fcf1665360dd71f73937f769c43b52
2021-12-14 09:25:19 +01:00
Yann Gautier 737ad29bf9 feat(stm32_gpio): add a function to reset a pin
Add set_gpio_reset_cfg() to set a pin in its reset configuration:
analog, no-pull, speed low, and its secure configuration, thanks to
stm32_gpio_is_secure_at_reset().

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b73c3636859f97fcc57f81cf68b42efc727922e
2021-12-14 09:25:19 +01:00
Yann Gautier ce21ee89d4 refactor(stm32mp1): sort compilation flags
Sort the compilation flags in platform.mk when checking and defining
them for C files.

Change-Id: I5a08399c89ede4c0bd8697045706122732205db5
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier c10f3a4559 feat(stm32mp1): add sign-compare warning
Add -Wsign-compare to TF_CFLAGS to check signedness comparison during
STM32MP1 platform compilation.

Change-Id: I4cada49622f44258d3e0da4560a566de9c7d54b3
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-14 09:25:19 +01:00
Yann Gautier b706608642 feat(stm32mp1): skip TOS_FW_CONFIG if not in FIP
Thanks to dyn_cfg_dtb_info_get_index(), we can check if TOS_FW_CONFIG
is inside the FIP partition. If not we can skip its treatment when
populating FIP images.

Change-Id: If5623eabd1ba484549d4a908d4a6f43325b36875
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-12-13 17:37:57 +01:00
Madhukar Pappireddy 714ca37dc7 Merge "feat(plat/zynqmp): disable the -mbranch-protection flag" into integration 2021-12-10 19:07:40 +01:00
Manish Pandey c6b2919834 Merge changes from topic "mb_critical_data" into integration
* changes:
  docs(measured-boot): add a platform function for critical data
  feat(fvp): measure critical data
2021-12-10 14:37:06 +01:00
Venkatesh Yadav Abbarapu 67abd4762b feat(plat/zynqmp): disable the -mbranch-protection flag
With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP uses the ARMv8 architecture,
so there is no impact when we disable the branch protection.
These instructions do not provide the branch protection in
architectures before Armv8.3-A.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I36f7a55abf99f50df2ee265255598d83b1f480c6
2021-12-10 05:16:07 -07:00
Madhukar Pappireddy 97af8baf0a Merge "refactor(measured-boot): add generic macros for using Crypto library" into integration 2021-12-10 01:25:26 +01:00
Madhukar Pappireddy 4f53c1301c Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN" into integration 2021-12-09 15:03:19 +01:00
Madhukar Pappireddy 590fd53d61 Merge "refactor(plat/synquacer): update PSCI system_off handling" into integration 2021-12-09 15:03:06 +01:00
Manish V Badarkhe cf21064ec8 feat(fvp): measure critical data
Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_finish' function invokes this platform function
immediately after populating the critical data.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia198295c6e07ab26d436eab1ff90df2cf28303af
2021-12-08 13:08:17 +00:00
Manish V Badarkhe 14db963fd3 refactor(measured-boot): add generic macros for using Crypto library
It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735
2021-12-08 11:00:13 +00:00
Sandrine Bailleux 0628fe3fff Merge "refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID" into integration 2021-12-08 08:16:53 +01:00
Masahisa Kojima e01acbe903 refactor(plat/synquacer): update PSCI system_off handling
SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP)
which manages system power.
This commit modifies the PSCI system_off handling to call SCMI,
same as other PSCI calls. System power-off is done by turing off
the ATX power supply through GPIO, this operation is transferred
to SCP.

Note that this commit modifies only the SCMI case, obsolete SCPI
implementation is not updated.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd
2021-12-07 17:33:29 +09:00
Masahisa Kojima 4d4911d77d fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN
The GTimer implemented on SynQuacer has similar issue found on Juno
wherein CNTBaseN.CNTFRQ can be written but does not reflect the value
of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM
in that the value updated in CNTCTLBase.CNTFRQ is not reflected
in CNTBaseN.CNTFRQ.

Hence enable the workaround (applied to Juno) for SynQuacer that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I5204fb57f28c0945812814f008c4905ef0882e2b
2021-12-07 17:29:27 +09:00
Madhukar Pappireddy 7c62111381 Merge changes from topic "st_uart" into integration
* changes:
  feat(plat/st): add STM32MP_UART_PROGRAMMER target
  feat(plat/st): add STM32CubeProgrammer support on UART
  feat(drivers/st/uart): add uart driver for STM32MP1
2021-12-06 19:03:26 +01:00
Tinghan Shen 690cb1265e feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP
1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204347737
TEST=build pass

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc
2021-12-06 15:29:08 +08:00
Tinghan Shen 20ef588e86 feat(plat/mediatek/mt8195): dump EMI MPU configurations
Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
2021-12-06 15:29:06 +08:00
Manish Pandey 8a63739b31 Merge "fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds" into integration 2021-12-03 15:12:21 +01:00
Patrick Delaunay 9083fa11ea feat(plat/st): add STM32MP_UART_PROGRAMMER target
Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.

Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ibd719dd46a11da78633728675ef6639635b6cf67
2021-12-03 09:26:11 +01:00
Patrick Delaunay fb3e7985c9 feat(plat/st): add STM32CubeProgrammer support on UART
Add a file to support the STMicroelectronics tool STM32CubeProgrammer
over UART in BL2 for STM32MP15x platform.

This tools is based on protocol defined in AN5275,
"USB DFU/USART protocols used in STM32MP1 Series bootloaders"
based on STM32 MCU protocols (AN3155, "USART protocol used
in the STM32 bootloader").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I956c95d8de0a94d1eb8e61f043651dae7b838170
2021-12-03 09:26:11 +01:00
Pali Rohár a4d35ff381 feat(plat/marvell/a3k): add north and south bridge reset registers
These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular bit,
but some need setting the bit. Reflect this via "_N" suffix in macro
names.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc
2021-12-02 17:37:58 +01:00
Vijayenthiran Subramaniam 78d7e81979 fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds
Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is set to
0 when SPM_MM build is enabled. To support SPM_MM builds on SGI/RD
platforms set ENABLE_SVE_FOR_NS to 0.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If78ed7567f6d988795b2bc7f772a883783246964
2021-12-02 08:27:51 +01:00
Manish Pandey 29ad12a7b5 Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration
* changes:
  fix(plat/xilinx/versal): resolve misra R10.6
  fix(plat/xilinx/versal): resolve misra R14.4
  fix(plat/xilinx/versal): resolve misra R17.7
  fix(plat/xilinx/versal): resolve misra R10.3
  fix(plat/xilinx/versal): resolve misra R7.2
  fix(plat/xilinx/versal): resolve misra R15.7
  fix(plat/xilinx/versal): resolve misra R15.6
  fix(plat/xilinx/versal): resolve misra R10.1 in pm services
  fix(plat/xilinx/versal): resolve misra R20.7 in pm services
  fix(plat/xilinx/versal): resolve misra R10.3 in pm services
  fix(plat/xilinx/versal): resolve misra R10.6 in pm services
  fix(plat/xilinx/versal): resolve misra R16.3 in pm services
  fix(plat/xilinx/versal): resolve misra R15.6 in pm services
2021-12-01 17:52:30 +01:00
Rex-BC Chen 27132f13ca feat(mt8186): initialize platform for MediaTek MT8186
- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5
2021-12-01 16:36:28 +01:00
Manish Pandey 2141a68543 Merge changes I0c1f7d6c,I3bec0b58,If24cf213 into integration
* changes:
  feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
  feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
  feat(plat/mediatek/apu): add mt8195 APU iommap regions
2021-12-01 14:21:50 +01:00
Abhyuday Godhasara 93d4625627 fix(plat/xilinx/versal): resolve misra R10.6
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
  with wider essential type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Ia0d13c3cfeb13d22b6fc7e8869cc713218302973
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara a62c40d427 fix(plat/xilinx/versal): resolve misra R14.4
MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
  expression of an iteration-statement shall have essentially Boolean type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I8cf821a42015858200cc0c514600012c8f61061f
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 526a1fd147 fix(plat/xilinx/versal): resolve misra R17.7
MISRA Violation: MISRA-C:2012 R.17.7
- The value returned by a function having non-void return type shall be
  used ((void) missing for discarded return value.).

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I1e6a598b9fe6c571a3e5010ee832ef860dfe491d
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara b2bb3efb8f fix(plat/xilinx/versal): resolve misra R10.3
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
  narrower essential type or of a different essential type category

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I9c6dd8dba40db8067b46947ceff295732648612a
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 0623dcea0f fix(plat/xilinx/versal): resolve misra R7.2
MISRA Violation: MISRA-C:2012 R.7.2
- A "u" or "U" suffix shall be applied to all integer constants that are
  represented in an unsigned type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iaf6db75e42913ddceccb803426287d0c47d7f31d
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara bc2637e379 fix(plat/xilinx/versal): resolve misra R15.7
MISRA Violation: MISRA-C:2012 R.15.7
- All if . . else if constructs shall be terminated with an else statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Iea32e32b5683f7accd7fac8d557957f05ed0f5c5
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara b9fa2d9fc1 fix(plat/xilinx/versal): resolve misra R15.6
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: If1ccaa2f254ac85a329295de501e2b5558e8ff43
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 775bf1bbd3 fix(plat/xilinx/versal): resolve misra R10.1 in pm services
MISRA Violation: MISRA-C:2012 R.10.1
- Operands shall not be of an inappropriate essential type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67b5788054a136be8d764472c5d85528a5c4272f
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 5dada6227b fix(plat/xilinx/versal): resolve misra R20.7 in pm services
MISRA Violation: MISRA-C:2012 R.20.7
- Expressions resulting from the expansion of macro parameters shall be
  enclosed in parentheses

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Id913c556cab955c798809ad2bd08ca3e48e2231a
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 5d1c211e22 fix(plat/xilinx/versal): resolve misra R10.3 in pm services
MISRA Violation: MISRA-C:2012 R.10.3
- The value of an expression shall not be assigned to an object with a
  narrower essential type or of a different essential type category

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I73c056ff4df2f14e04c92a49ac5c97e578e82107
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara fa98d7f2f8 fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
  with wider essential type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67ac6b6b4b643f57e76a435345540e241c9a88b9
2021-11-30 02:00:01 -08:00
Abhyuday Godhasara 27ae531088 fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I576b2c6eb7d1b7ef20440b9a616886ccf230b63e
2021-11-30 01:59:34 -08:00
Abhyuday Godhasara 4156719550 fix(plat/xilinx/versal): resolve misra R15.6 in pm services
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
  a compound statement

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I82e924a77ee3afeb56fa18714e94cc4f6fff5a49
2021-11-30 01:54:51 -08:00
Flora Fu 296b590206 feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
The clock and pll of mt8195 can be locked into security access
by device apc. Add clock and pll related SiP call for the access
from Kernel space.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I0c1f7d6c6abdd3b976492a0b776dc5b1d1f1512b
2021-11-30 09:34:05 +08:00
Flora Fu 88906b4437 feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
Add APU SiP call support for start/stop mcu.

Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: I3bec0b588a2884327ba645e9568c0150436afa42
2021-11-30 09:23:46 +08:00