Derek Basehore 5a5dc61713 rockchip: rk3399: Fix CAS latency setting ... The F1 CAS latency setting was not bit shifted, which resulted in setting the DRAM additive latency value instead. Signed-off-by: Derek Basehore <dbasehore@chromium.org>		2017-02-24 20:07:45 +08:00
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drivers	rockchip: rk3399: Fix CAS latency setting	2017-02-24 20:07:45 +08:00
include	rockchip: rk3399: sperate the BL31 parameters for sharing	2017-02-24 20:07:44 +08:00
plat_sip_calls.c	rk3399: dram: use PMU M0 to do ddr frequency scaling	2017-02-24 20:07:44 +08:00
platform.mk	rockchip: rk3399: Clean up and seprate secure parts from SoC codes	2017-02-24 20:07:45 +08:00
rk3399_def.h	rockchip: Clean up header and referenced files	2017-02-24 20:07:44 +08:00